{"id":"https://openalex.org/W2134834716","doi":"https://doi.org/10.1109/eh.2004.1310805","title":"Evolution based synthesis of analog integrated circuits and systems","display_name":"Evolution based synthesis of analog integrated circuits and systems","publication_year":2004,"publication_date":"2004-11-13","ids":{"openalex":"https://openalex.org/W2134834716","doi":"https://doi.org/10.1109/eh.2004.1310805","mag":"2134834716"},"language":"en","primary_location":{"id":"doi:10.1109/eh.2004.1310805","is_oa":false,"landing_page_url":"https://doi.org/10.1109/eh.2004.1310805","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 2004 NASA/DoD Conference on Evolvable Hardware, 2004.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051590590","display_name":"Sina Balk\u0131r","orcid":null},"institutions":[{"id":"https://openalex.org/I114395901","display_name":"University of Nebraska\u2013Lincoln","ror":"https://ror.org/043mer456","country_code":"US","type":"education","lineage":["https://openalex.org/I114395901"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Balkir","raw_affiliation_strings":["Department of Electrical Engineering, 209N WSEC, University of Nebraska, Lincoln, Lincolnshire, NE, USA","Dept. of Electr. Eng., Nebraska Univ., Lincoln, NE, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, 209N WSEC, University of Nebraska, Lincoln, Lincolnshire, NE, USA","institution_ids":["https://openalex.org/I114395901"]},{"raw_affiliation_string":"Dept. of Electr. Eng., Nebraska Univ., Lincoln, NE, USA","institution_ids":["https://openalex.org/I114395901"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052669741","display_name":"G\u00fcnhan D\u00fcndar","orcid":"https://orcid.org/0000-0003-2044-2706"},"institutions":[{"id":"https://openalex.org/I114395901","display_name":"University of Nebraska\u2013Lincoln","ror":"https://ror.org/043mer456","country_code":"US","type":"education","lineage":["https://openalex.org/I114395901"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"G. Dundar","raw_affiliation_strings":["Department of Electrical Engineering, 209N WSEC, University of Nebraska, Lincoln, Lincolnshire, NE, USA","[Department of Electrical Engineering, 209N WSEC, University of Nebraska, Lincoln, Lincolnshire, NE, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, 209N WSEC, University of Nebraska, Lincoln, Lincolnshire, NE, USA","institution_ids":["https://openalex.org/I114395901"]},{"raw_affiliation_string":"[Department of Electrical Engineering, 209N WSEC, University of Nebraska, Lincoln, Lincolnshire, NE, USA]","institution_ids":["https://openalex.org/I114395901"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5080597481","display_name":"G. Alpayd\u0131n","orcid":null},"institutions":[{"id":"https://openalex.org/I114395901","display_name":"University of Nebraska\u2013Lincoln","ror":"https://ror.org/043mer456","country_code":"US","type":"education","lineage":["https://openalex.org/I114395901"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"G. Alpaydin","raw_affiliation_strings":["Department of Electrical Engineering, 209N WSEC, University of Nebraska, Lincoln, Lincolnshire, NE, USA","[Department of Electrical Engineering, 209N WSEC, University of Nebraska, Lincoln, Lincolnshire, NE, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, 209N WSEC, University of Nebraska, Lincoln, Lincolnshire, NE, USA","institution_ids":["https://openalex.org/I114395901"]},{"raw_affiliation_string":"[Department of Electrical Engineering, 209N WSEC, University of Nebraska, Lincoln, Lincolnshire, NE, USA]","institution_ids":["https://openalex.org/I114395901"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I114395901"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"26","last_page":"29"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9908999800682068,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10100","display_name":"Metaheuristic Optimization Algorithms Research","score":0.9718000292778015,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6846835613250732},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.6353594660758972},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.6324772834777832},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.6265643239021301},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.49885010719299316},{"id":"https://openalex.org/keywords/feature","display_name":"Feature (linguistics)","score":0.4931616187095642},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.49123209714889526},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4395018219947815},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4390358030796051},{"id":"https://openalex.org/keywords/fuzzy-logic","display_name":"Fuzzy logic","score":0.4307316243648529},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.30412885546684265},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.26942020654678345},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18600451946258545},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.16320303082466125},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1211894154548645}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6846835613250732},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.6353594660758972},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.6324772834777832},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.6265643239021301},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.49885010719299316},{"id":"https://openalex.org/C2776401178","wikidata":"https://www.wikidata.org/wiki/Q12050496","display_name":"Feature (linguistics)","level":2,"score":0.4931616187095642},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.49123209714889526},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4395018219947815},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4390358030796051},{"id":"https://openalex.org/C58166","wikidata":"https://www.wikidata.org/wiki/Q224821","display_name":"Fuzzy logic","level":2,"score":0.4307316243648529},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.30412885546684265},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.26942020654678345},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18600451946258545},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.16320303082466125},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1211894154548645},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/eh.2004.1310805","is_oa":false,"landing_page_url":"https://doi.org/10.1109/eh.2004.1310805","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 2004 NASA/DoD Conference on Evolvable Hardware, 2004.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2102635904","https://openalex.org/W2108732866","https://openalex.org/W2110033475","https://openalex.org/W2112628016","https://openalex.org/W2140823559","https://openalex.org/W2146527760","https://openalex.org/W2147137877","https://openalex.org/W2159880432","https://openalex.org/W2170444246"],"related_works":["https://openalex.org/W2204879205","https://openalex.org/W2096437374","https://openalex.org/W1943174035","https://openalex.org/W1928481607","https://openalex.org/W3135165657","https://openalex.org/W1485582195","https://openalex.org/W57337972","https://openalex.org/W2313216219","https://openalex.org/W1561306903","https://openalex.org/W4318953393"],"abstract_inverted_index":{"An":[0,17],"evolutionary":[1,34],"approach":[2,112],"to":[3,99],"automatic":[4],"synthesis":[5,94,111],"of":[6,20,33,46,62,82,88,91,102],"analog":[7,42,122],"integrated":[8],"circuits":[9],"and":[10,36],"systems":[11],"is":[12,23,49,65,85,113],"presented":[13],"in":[14],"this":[15,21,58],"paper.":[16],"essential":[18],"feature":[19,81],"system":[22,84,95,118],"a":[24,52,100],"high":[25],"performance":[26,74],"optimization":[27],"algorithm":[28],"based":[29],"on":[30,108],"the":[31,83,86,117],"combination":[32],"strategies":[35],"simulated":[37],"annealing.":[38],"As":[39],"required":[40],"by":[41],"circuit":[43],"synthesis,":[44],"modeling":[45,61],"DC":[47,54],"parameters":[48,64],"done":[50,66],"via":[51],"fast":[53],"simulator":[55],"developed":[56],"for":[57,120],"purpose":[59],"whereas":[60],"AC":[63],"either":[67],"with":[68,72,105],"user-defined":[69],"equations":[70],"or":[71],"neural-fuzzy":[73],"models":[75],"trained":[76],"from":[77],"SPICE":[78],"simulations.":[79],"Another":[80],"incorporation":[87],"matching":[89],"properties":[90],"devices.":[92],"The":[93,110],"has":[96],"been":[97],"applied":[98],"number":[101],"design":[103],"cases":[104],"demonstrated":[106],"validity":[107],"silicon.":[109],"also":[114],"considered":[115],"at":[116],"level":[119],"potential":[121],"VLSI":[123],"applications.":[124]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}