{"id":"https://openalex.org/W2131413888","doi":"https://doi.org/10.1109/eh.2003.1217664","title":"Exploring FPGA structures for evolving fault tolerant hardware","display_name":"Exploring FPGA structures for evolving fault tolerant hardware","publication_year":2003,"publication_date":"2003-11-04","ids":{"openalex":"https://openalex.org/W2131413888","doi":"https://doi.org/10.1109/eh.2003.1217664","mag":"2131413888"},"language":"en","primary_location":{"id":"doi:10.1109/eh.2003.1217664","is_oa":false,"landing_page_url":"https://doi.org/10.1109/eh.2003.1217664","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010681007","display_name":"A. P. Shanthi","orcid":null},"institutions":[{"id":"https://openalex.org/I33585257","display_name":"Anna University, Chennai","ror":"https://ror.org/01qhf1r47","country_code":"IN","type":"education","lineage":["https://openalex.org/I33585257"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"A.P. Shanthi","raw_affiliation_strings":["School of Computer Science and Engineering, Anna University, Chennai, India","Sch. of Comput. Sci. & Eng., Anna Univ., India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Science and Engineering, Anna University, Chennai, India","institution_ids":["https://openalex.org/I33585257"]},{"raw_affiliation_string":"Sch. of Comput. Sci. & Eng., Anna Univ., India","institution_ids":["https://openalex.org/I33585257"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002422673","display_name":"Ramakrishnan Parthasarathi","orcid":"https://orcid.org/0000-0001-5417-5867"},"institutions":[{"id":"https://openalex.org/I33585257","display_name":"Anna University, Chennai","ror":"https://ror.org/01qhf1r47","country_code":"IN","type":"education","lineage":["https://openalex.org/I33585257"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"R. Parthasarathi","raw_affiliation_strings":["School of Computer Science and Engineering, Anna University, Chennai, India","Sch. of Comput. Sci. & Eng., Anna Univ., India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Science and Engineering, Anna University, Chennai, India","institution_ids":["https://openalex.org/I33585257"]},{"raw_affiliation_string":"Sch. of Comput. Sci. & Eng., Anna Univ., India","institution_ids":["https://openalex.org/I33585257"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.813,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.91575273,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"174","last_page":"181"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10100","display_name":"Metaheuristic Optimization Algorithms Research","score":0.9914000034332275,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10621","display_name":"Gene Regulatory Network Analysis","score":0.958299994468689,"subfield":{"id":"https://openalex.org/subfields/1312","display_name":"Molecular Biology"},"field":{"id":"https://openalex.org/fields/13","display_name":"Biochemistry, Genetics and Molecular Biology"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7968683838844299},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7227351665496826},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.6846479177474976},{"id":"https://openalex.org/keywords/evolvable-hardware","display_name":"Evolvable hardware","score":0.6560256481170654},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.6213564872741699},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5822222232818604},{"id":"https://openalex.org/keywords/granularity","display_name":"Granularity","score":0.5704867243766785},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.5511847138404846},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5224265456199646},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.5204015970230103},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4893893599510193},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4467575252056122},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.43300461769104004},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.43044567108154297},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4113551676273346},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3789626359939575},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.35103076696395874},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2180461287498474},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.1813836693763733},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12010404467582703}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7968683838844299},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7227351665496826},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.6846479177474976},{"id":"https://openalex.org/C2776243922","wikidata":"https://www.wikidata.org/wiki/Q5418727","display_name":"Evolvable hardware","level":3,"score":0.6560256481170654},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.6213564872741699},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5822222232818604},{"id":"https://openalex.org/C177774035","wikidata":"https://www.wikidata.org/wiki/Q1246948","display_name":"Granularity","level":2,"score":0.5704867243766785},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.5511847138404846},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5224265456199646},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.5204015970230103},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4893893599510193},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4467575252056122},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.43300461769104004},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.43044567108154297},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4113551676273346},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3789626359939575},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.35103076696395874},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2180461287498474},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.1813836693763733},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12010404467582703},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/eh.2003.1217664","is_oa":false,"landing_page_url":"https://doi.org/10.1109/eh.2003.1217664","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1495408842","https://openalex.org/W1510718579","https://openalex.org/W1544659150","https://openalex.org/W1742387217","https://openalex.org/W1961642580","https://openalex.org/W2000330859","https://openalex.org/W2051179702","https://openalex.org/W2117357818","https://openalex.org/W2118715054","https://openalex.org/W2134617048","https://openalex.org/W6629665985","https://openalex.org/W6637871879","https://openalex.org/W6680149937"],"related_works":["https://openalex.org/W29481652","https://openalex.org/W2069145203","https://openalex.org/W2085176210","https://openalex.org/W1702800398","https://openalex.org/W2106889348","https://openalex.org/W2083793411","https://openalex.org/W2135500595","https://openalex.org/W2543766998","https://openalex.org/W573124066","https://openalex.org/W1592424226"],"abstract_inverted_index":{"This":[0,33],"work":[1],"explores":[2],"different":[3],"types":[4],"of":[5,74,86,92,104],"FPGA":[6,57],"(field":[7],"programmable":[8],"gate":[9],"array)":[10],"structures":[11],"for":[12,20,80,99,116,129],"evolving":[13],"fault":[14,22,100],"tolerant":[15],"hardware.":[16],"A":[17],"three-tier":[18],"model":[19,34],"providing":[21],"tolerance":[23],"to":[24,70,96,111],"the":[25,36,42,50,56,62,72,77,81,84,87,90,113],"digital":[26],"circuits":[27,65],"evolved":[28,98],"on":[29,76],"FPGAs":[30],"is":[31,124],"proposed.":[32],"combines":[35],"process":[37],"level":[38,52],"redundancy":[39,53],"provided":[40],"by":[41,55],"GA":[43],"(genetic":[44],"algorithm)":[45],"based":[46],"evolution":[47,82,88,117],"techniques":[48],"and":[49,89,108],"structural":[51],"supported":[54],"architectures.":[58],"Simulation":[59],"results":[60],"using":[61,105],"ISCAS'89":[63],"benchmark":[64],"have":[66],"been":[67,119],"carried":[68],"out":[69],"study":[71],"effect":[73,103],"granularity":[75],"time":[78,114],"taken":[79,115],"process,":[83],"dimensionality":[85],"number":[91],"solutions":[93],"that":[94,122],"need":[95],"be":[97],"coverage.":[101],"The":[102],"a":[106,125],"divide":[107],"conquer":[109],"approach":[110,127],"reduce":[112],"has":[118],"studied":[120],"proving":[121],"this":[123],"feasible":[126],"even":[128],"complex":[130],"circuits.":[131]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}