{"id":"https://openalex.org/W2148348448","doi":"https://doi.org/10.1109/eh.2003.1217635","title":"Comparing different serial and parallel heuristics to design combinational logic circuits","display_name":"Comparing different serial and parallel heuristics to design combinational logic circuits","publication_year":2003,"publication_date":"2003-11-04","ids":{"openalex":"https://openalex.org/W2148348448","doi":"https://doi.org/10.1109/eh.2003.1217635","mag":"2148348448"},"language":"en","primary_location":{"id":"doi:10.1109/eh.2003.1217635","is_oa":false,"landing_page_url":"https://doi.org/10.1109/eh.2003.1217635","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5085548317","display_name":"Carlos A. Coello Coello","orcid":"https://orcid.org/0000-0002-8435-680X"},"institutions":[{"id":"https://openalex.org/I68368234","display_name":"Centro de Investigaci\u00f3n y de Estudios Avanzados del Instituto Polit\u00e9cnico Nacional","ror":"https://ror.org/009eqmr18","country_code":"MX","type":"facility","lineage":["https://openalex.org/I59361560","https://openalex.org/I68368234"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"C.A.C. Coello","raw_affiliation_strings":["Evolutionary Computation Group, Dpto. de Ingenier\u00eda El\u00e9ctrica, Secci\u00f3n Computaci\u00f3n, CINVESTAV, Mexicali, Mexico"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Evolutionary Computation Group, Dpto. de Ingenier\u00eda El\u00e9ctrica, Secci\u00f3n Computaci\u00f3n, CINVESTAV, Mexicali, Mexico","institution_ids":["https://openalex.org/I68368234"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019440355","display_name":"Enrique Alba","orcid":"https://orcid.org/0000-0002-5520-8875"},"institutions":[{"id":"https://openalex.org/I82767444","display_name":"Universidad de M\u00e1laga","ror":"https://ror.org/036b2ww28","country_code":"ES","type":"education","lineage":["https://openalex.org/I82767444"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"E. Alba","raw_affiliation_strings":["Dpto. de Lenguajes y Ciencias de la Computaci\u00f3n, E. T. S. Ingenier\u00eda Inform\u00e0tica, Malaga, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dpto. de Lenguajes y Ciencias de la Computaci\u00f3n, E. T. S. Ingenier\u00eda Inform\u00e0tica, Malaga, Spain","institution_ids":["https://openalex.org/I82767444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007483425","display_name":"Gabriel Luque","orcid":"https://orcid.org/0000-0001-7909-1416"},"institutions":[{"id":"https://openalex.org/I82767444","display_name":"Universidad de M\u00e1laga","ror":"https://ror.org/036b2ww28","country_code":"ES","type":"education","lineage":["https://openalex.org/I82767444"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"G. Luque","raw_affiliation_strings":["Dpto. de Lenguajes y Ciencias de la Computaci\u00f3n, E. T. S. Ingenier\u00eda Inform\u00e0tica, Malaga, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dpto. de Lenguajes y Ciencias de la Computaci\u00f3n, E. T. S. Ingenier\u00eda Inform\u00e0tica, Malaga, Spain","institution_ids":["https://openalex.org/I82767444"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.9377,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.82341516,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"3","last_page":"12"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10100","display_name":"Metaheuristic Optimization Algorithms Research","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9932000041007996,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/heuristics","display_name":"Heuristics","score":0.814434289932251},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.8024485111236572},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.7354567050933838},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7279846668243408},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.7233753204345703},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6267555356025696},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.5750026702880859},{"id":"https://openalex.org/keywords/genetic-algorithm","display_name":"Genetic algorithm","score":0.5230063796043396},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5180028080940247},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.49178507924079895},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4399245083332062},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4357191026210785},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4330154061317444},{"id":"https://openalex.org/keywords/machine-learning","display_name":"Machine learning","score":0.058995068073272705}],"concepts":[{"id":"https://openalex.org/C127705205","wikidata":"https://www.wikidata.org/wiki/Q5748245","display_name":"Heuristics","level":2,"score":0.814434289932251},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.8024485111236572},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.7354567050933838},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7279846668243408},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.7233753204345703},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6267555356025696},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.5750026702880859},{"id":"https://openalex.org/C8880873","wikidata":"https://www.wikidata.org/wiki/Q187787","display_name":"Genetic algorithm","level":2,"score":0.5230063796043396},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5180028080940247},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.49178507924079895},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4399245083332062},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4357191026210785},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4330154061317444},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.058995068073272705},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/eh.2003.1217635","is_oa":false,"landing_page_url":"https://doi.org/10.1109/eh.2003.1217635","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320321739","display_name":"Consejo Nacional de Ciencia y Tecnolog\u00eda","ror":"https://ror.org/059ex5q34"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W31528042","https://openalex.org/W43207804","https://openalex.org/W1486894692","https://openalex.org/W1514048016","https://openalex.org/W1604160780","https://openalex.org/W2003243598","https://openalex.org/W2024060531","https://openalex.org/W2030557043","https://openalex.org/W2056760934","https://openalex.org/W2083294917","https://openalex.org/W2109069188","https://openalex.org/W2137702546","https://openalex.org/W2149950399","https://openalex.org/W2166348281","https://openalex.org/W2325535142","https://openalex.org/W2914275007","https://openalex.org/W4233183865","https://openalex.org/W6601312733","https://openalex.org/W6601734986","https://openalex.org/W6758750208"],"related_works":["https://openalex.org/W29481652","https://openalex.org/W4248668797","https://openalex.org/W2110968362","https://openalex.org/W4238178324","https://openalex.org/W3141297747","https://openalex.org/W818963952","https://openalex.org/W1939541994","https://openalex.org/W1603944672","https://openalex.org/W1851795671","https://openalex.org/W2146663621"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"perform":[4],"a":[5,24,44,47,65],"comparative":[6],"study":[7,38],"of":[8,19,30,33,46,59,80],"different":[9],"heuristics":[10],"used":[11],"to":[12,76],"design":[13],"combinational":[14],"logic":[15],"circuits.":[16],"The":[17],"use":[18,58],"local":[20],"search":[21],"hybridized":[22],"with":[23,50],"genetic":[25,48],"algorithm":[26,49],"and":[27,55],"the":[28,37,57,70,78,81],"effect":[29],"parallelism":[31,60],"are":[32],"particular":[34],"interest":[35],"in":[36,69],"conducted.":[39],"Our":[40],"results":[41],"indicate":[42],"that":[43,56],"hybridization":[45],"simulated":[51],"annealing":[52],"is":[53],"beneficial":[54],"does":[61],"not":[62],"only":[63],"introduce":[64],"speedup":[66],"(as":[67],"expected)":[68],"algorithms,":[71],"but":[72],"also":[73],"allows":[74],"one":[75],"improve":[77],"quality":[79],"solutions":[82],"found.":[83]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2013,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}