{"id":"https://openalex.org/W2017952864","doi":"https://doi.org/10.1109/educon.2012.6201037","title":"Internet based support tool for the teaching and learning of the IEEE standard 1500 for embedded core-based integrated circuits","display_name":"Internet based support tool for the teaching and learning of the IEEE standard 1500 for embedded core-based integrated circuits","publication_year":2012,"publication_date":"2012-04-01","ids":{"openalex":"https://openalex.org/W2017952864","doi":"https://doi.org/10.1109/educon.2012.6201037","mag":"2017952864"},"language":"en","primary_location":{"id":"doi:10.1109/educon.2012.6201037","is_oa":false,"landing_page_url":"https://doi.org/10.1109/educon.2012.6201037","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2012 IEEE Global Engineering Education Conference (EDUCON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053889011","display_name":"Ian Grout","orcid":"https://orcid.org/0000-0003-1462-0481"},"institutions":[{"id":"https://openalex.org/I230495080","display_name":"University of Limerick","ror":"https://ror.org/00a0n9e72","country_code":"IE","type":"education","lineage":["https://openalex.org/I230495080"]}],"countries":["IE"],"is_corresponding":true,"raw_author_name":"Ian Grout","raw_affiliation_strings":["University of Limerick, Limerick, IE","Department of Electronic & Computer, Engineering, University of Limerick, IRELAND"],"affiliations":[{"raw_affiliation_string":"University of Limerick, Limerick, IE","institution_ids":["https://openalex.org/I230495080"]},{"raw_affiliation_string":"Department of Electronic & Computer, Engineering, University of Limerick, IRELAND","institution_ids":["https://openalex.org/I230495080"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040931536","display_name":"Abu Khari A\u2019ain","orcid":null},"institutions":[{"id":"https://openalex.org/I4576418","display_name":"University of Technology Malaysia","ror":"https://ror.org/026w31v75","country_code":"MY","type":"education","lineage":["https://openalex.org/I4576418"]}],"countries":["MY"],"is_corresponding":false,"raw_author_name":"Abu Khari Bin A'ain","raw_affiliation_strings":["Universiti Teknologi Malaysia, Skudai, Johor, MY","Faculty of Electrical Engineering, Universiti Teknologi Malaysia, Skudai, 81310 Johor, Malaysia"],"affiliations":[{"raw_affiliation_string":"Universiti Teknologi Malaysia, Skudai, Johor, MY","institution_ids":["https://openalex.org/I4576418"]},{"raw_affiliation_string":"Faculty of Electrical Engineering, Universiti Teknologi Malaysia, Skudai, 81310 Johor, Malaysia","institution_ids":["https://openalex.org/I4576418"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5053889011"],"corresponding_institution_ids":["https://openalex.org/I230495080"],"apc_list":null,"apc_paid":null,"fwci":0.53815809,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.66666667,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.8234308958053589},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.774611234664917},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7461913824081421},{"id":"https://openalex.org/keywords/the-internet","display_name":"The Internet","score":0.6400647759437561},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.6044262647628784},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.550314724445343},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.548371434211731},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.5189761519432068},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4705241918563843},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.4422356188297272},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.36035385727882385},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.19826146960258484},{"id":"https://openalex.org/keywords/world-wide-web","display_name":"World Wide Web","score":0.1673392653465271},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.15073302388191223},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12326407432556152},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.09878581762313843}],"concepts":[{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.8234308958053589},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.774611234664917},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7461913824081421},{"id":"https://openalex.org/C110875604","wikidata":"https://www.wikidata.org/wiki/Q75","display_name":"The Internet","level":2,"score":0.6400647759437561},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.6044262647628784},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.550314724445343},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.548371434211731},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.5189761519432068},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4705241918563843},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.4422356188297272},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.36035385727882385},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.19826146960258484},{"id":"https://openalex.org/C136764020","wikidata":"https://www.wikidata.org/wiki/Q466","display_name":"World Wide Web","level":1,"score":0.1673392653465271},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15073302388191223},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12326407432556152},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.09878581762313843},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/educon.2012.6201037","is_oa":false,"landing_page_url":"https://doi.org/10.1109/educon.2012.6201037","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2012 IEEE Global Engineering Education Conference (EDUCON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.44999998807907104,"id":"https://metadata.un.org/sdg/4","display_name":"Quality Education"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W1885886925","https://openalex.org/W2067714421","https://openalex.org/W2165749494"],"related_works":["https://openalex.org/W2110818533","https://openalex.org/W2107525390","https://openalex.org/W1917852300","https://openalex.org/W2384838054","https://openalex.org/W2139058049","https://openalex.org/W2157191248","https://openalex.org/W2376018793","https://openalex.org/W2548456620","https://openalex.org/W2122949436","https://openalex.org/W78782492"],"abstract_inverted_index":{"In":[0],"this":[1,88,128],"paper,":[2],"an":[3,38],"education":[4],"tool":[5,36,42,61,89,97],"for":[6,86],"assisting":[7],"the":[8,13,22,45,52,63,71,75,79,100,105,113,117,125,133],"teaching":[9,101],"and":[10,33,54,74,102,107,110],"learning":[11,96,103],"of":[12,24,51,69,104,119,127,135],"IEEE":[14],"1500":[15],"standard":[16,53,106,129],"testability":[17,130],"method,":[18],"used":[19],"to":[20,47,57,65,91,98,111,115],"support":[21,99],"testing":[23],"complex":[25],"system-on-a-chip":[26],"(SoC)":[27],"integrated":[28,120],"circuits":[29,121],"(ICs),":[30],"is":[31,37],"developed":[32],"presented.":[34],"The":[35,60,83],"Internet":[39,80],"browser":[40,81],"based":[41,95],"that":[43,122],"supports":[44],"ability":[46],"investigate":[48,116],"key":[49,84],"aspects":[50],"its":[55,108],"application":[56],"IC":[58],"designs.":[59],"allows":[62],"user":[64],"create":[66],"VHDL":[67,136],"descriptions":[68],"both":[70],"test":[72],"circuitry":[73,77],"function":[76],"via":[78],"interface.":[82],"considerations":[85],"developing":[87],"were":[90],"provide":[92],"a":[93],"computer":[94],"application,":[109],"allow":[112],"learner":[114],"design":[118],"would":[123],"require":[124],"use":[126,134],"method":[131],"through":[132],"(VHSIC":[137],"hardware":[138],"description":[139],"language":[140],"(HDL)).":[141]},"counts_by_year":[{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}