{"id":"https://openalex.org/W3092567711","doi":"https://doi.org/10.1109/ecctd49232.2020.9218420","title":"Implementation of Logical and Memory Functions with Memristor Cellular Nonlinear Networks","display_name":"Implementation of Logical and Memory Functions with Memristor Cellular Nonlinear Networks","publication_year":2020,"publication_date":"2020-09-01","ids":{"openalex":"https://openalex.org/W3092567711","doi":"https://doi.org/10.1109/ecctd49232.2020.9218420","mag":"3092567711"},"language":"en","primary_location":{"id":"doi:10.1109/ecctd49232.2020.9218420","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd49232.2020.9218420","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 European Conference on Circuit Theory and Design (ECCTD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5023152110","display_name":"Alon Ascoli","orcid":"https://orcid.org/0000-0003-4026-9648"},"institutions":[{"id":"https://openalex.org/I60587646","display_name":"Brno University of Technology","ror":"https://ror.org/03613d656","country_code":"CZ","type":"education","lineage":["https://openalex.org/I60587646"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"A. Ascoli","raw_affiliation_strings":["Dept. of Microelectronics, Brno University of Technology, Brno, Czech Republic","Institute of Circuits and Systems, Faculty of Electrical and Computer Engineering, Technical University Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Microelectronics, Brno University of Technology, Brno, Czech Republic","institution_ids":["https://openalex.org/I60587646"]},{"raw_affiliation_string":"Institute of Circuits and Systems, Faculty of Electrical and Computer Engineering, Technical University Dresden, Dresden, Germany","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004169838","display_name":"Ioannis Messaris","orcid":"https://orcid.org/0000-0002-4286-6553"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"I. Messaris","raw_affiliation_strings":["Institute of Circuits and Systems, Faculty of Electrical and Computer Engineering, Technical University Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Circuits and Systems, Faculty of Electrical and Computer Engineering, Technical University Dresden, Dresden, Germany","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066450151","display_name":"Ahmet \u015eamil Demirkol","orcid":"https://orcid.org/0000-0002-1236-1300"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"A.S. Demirkol","raw_affiliation_strings":["Institute of Circuits and Systems, Faculty of Electrical and Computer Engineering, Technical University Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Circuits and Systems, Faculty of Electrical and Computer Engineering, Technical University Dresden, Dresden, Germany","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012451668","display_name":"Ronald Tetzlaff","orcid":"https://orcid.org/0000-0001-7436-0103"},"institutions":[{"id":"https://openalex.org/I60587646","display_name":"Brno University of Technology","ror":"https://ror.org/03613d656","country_code":"CZ","type":"education","lineage":["https://openalex.org/I60587646"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"R. Tetzlaff","raw_affiliation_strings":["Dept. of Microelectronics, Brno University of Technology, Brno, Czech Republic","Institute of Circuits and Systems, Faculty of Electrical and Computer Engineering, Technical University Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Microelectronics, Brno University of Technology, Brno, Czech Republic","institution_ids":["https://openalex.org/I60587646"]},{"raw_affiliation_string":"Institute of Circuits and Systems, Faculty of Electrical and Computer Engineering, Technical University Dresden, Dresden, Germany","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090657067","display_name":"Leon O. Chua","orcid":"https://orcid.org/0000-0002-1652-5464"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"L. Chua","raw_affiliation_strings":["Dept. of Electrical Engineering and Computer Sciences, University of California, Berkeley, Berkeley, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electrical Engineering and Computer Sciences, University of California, Berkeley, Berkeley, USA","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069658742","display_name":"Dalibor Biolek","orcid":"https://orcid.org/0000-0002-7607-6146"},"institutions":[{"id":"https://openalex.org/I60587646","display_name":"Brno University of Technology","ror":"https://ror.org/03613d656","country_code":"CZ","type":"education","lineage":["https://openalex.org/I60587646"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"D. Biolek","raw_affiliation_strings":["Dept. of Microelectronics, Brno University of Technology, Brno, Czech Republic"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Microelectronics, Brno University of Technology, Brno, Czech Republic","institution_ids":["https://openalex.org/I60587646"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083744068","display_name":"Viera Biolkov\u00e1","orcid":"https://orcid.org/0000-0003-2589-2722"},"institutions":[{"id":"https://openalex.org/I60587646","display_name":"Brno University of Technology","ror":"https://ror.org/03613d656","country_code":"CZ","type":"education","lineage":["https://openalex.org/I60587646"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"V. Biolkova","raw_affiliation_strings":["Dept. of Radio Electronics, Brno University of Technology, Brno, Czech Republic"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Radio Electronics, Brno University of Technology, Brno, Czech Republic","institution_ids":["https://openalex.org/I60587646"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066848813","display_name":"Zden\u011bk Kolka","orcid":"https://orcid.org/0000-0002-7034-9430"},"institutions":[{"id":"https://openalex.org/I60587646","display_name":"Brno University of Technology","ror":"https://ror.org/03613d656","country_code":"CZ","type":"education","lineage":["https://openalex.org/I60587646"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Z. Kolka","raw_affiliation_strings":["Dept. of Radio Electronics, Brno University of Technology, Brno, Czech Republic"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Radio Electronics, Brno University of Technology, Brno, Czech Republic","institution_ids":["https://openalex.org/I60587646"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":8,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.1041,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.44187902,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.9420870542526245},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7451751232147217},{"id":"https://openalex.org/keywords/nonlinear-system","display_name":"Nonlinear system","score":0.6231836080551147},{"id":"https://openalex.org/keywords/memistor","display_name":"Memistor","score":0.5149467587471008},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.45591413974761963},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4172058701515198},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.37466782331466675},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.3097383379936218},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.20181229710578918},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12507110834121704},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10618618130683899}],"concepts":[{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.9420870542526245},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7451751232147217},{"id":"https://openalex.org/C158622935","wikidata":"https://www.wikidata.org/wiki/Q660848","display_name":"Nonlinear system","level":2,"score":0.6231836080551147},{"id":"https://openalex.org/C1895703","wikidata":"https://www.wikidata.org/wiki/Q6034938","display_name":"Memistor","level":4,"score":0.5149467587471008},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.45591413974761963},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4172058701515198},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.37466782331466675},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.3097383379936218},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.20181229710578918},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12507110834121704},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10618618130683899},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ecctd49232.2020.9218420","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd49232.2020.9218420","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 European Conference on Circuit Theory and Design (ECCTD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.6200000047683716}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W69443694","https://openalex.org/W1995314879","https://openalex.org/W2019061854","https://openalex.org/W2027895023","https://openalex.org/W2030834420","https://openalex.org/W2047859916","https://openalex.org/W2069717653","https://openalex.org/W2094605391","https://openalex.org/W2292208776","https://openalex.org/W2295422590","https://openalex.org/W2407339173","https://openalex.org/W2500183209","https://openalex.org/W2603064927","https://openalex.org/W2900178210","https://openalex.org/W2977266164","https://openalex.org/W2997287227","https://openalex.org/W3014291826"],"related_works":["https://openalex.org/W3170109256","https://openalex.org/W2185262500","https://openalex.org/W4251693286","https://openalex.org/W1543954628","https://openalex.org/W4385367273","https://openalex.org/W2797315502","https://openalex.org/W2163054919","https://openalex.org/W4283019775","https://openalex.org/W3173413269","https://openalex.org/W4401034269"],"abstract_inverted_index":{"The":[0,100],"peculiar":[1],"combined":[2],"capability":[3],"of":[4,32,46,63,66,75,88,102,131,141,161,173,191],"nonvolatile":[5],"resistance":[6],"switching":[7],"memories":[8],"to":[9,21,71,82,110,151],"store":[10],"and":[11,34,51,86,117,143,169],"process":[12],"data":[13,177],"within":[14],"a":[15,153],"common":[16],"nanoscale":[17],"physical":[18],"medium":[19],"allows":[20],"implement":[22],"disruptive":[23],"mem-computing":[24,189],"paradigms":[25],"in":[26,96,104],"hybrid":[27],"circuits":[28],"leveraging":[29],"the":[30,40,43,61,72,76,84,129,139,159,170,179,187],"compatibility":[31],"CMOS":[33],"memristive":[35,89,180],"technologies.":[36],"This":[37,135],"may":[38],"pave":[39],"way":[41],"toward":[42],"future":[44],"development":[45],"minaturized,":[47],"lightweight,":[48],"ultra-dense,":[49],"high-speed":[50],"low-power":[52],"universal":[53],"memcomputers":[54],"with":[55],"sensing":[56],"functionality":[57],"on":[58,166],"board.":[59],"Since":[60],"availability":[62],"technical":[64],"products":[65],"this":[67],"kind":[68],"would":[69],"respond":[70],"current":[73],"demands":[74],"Internet-of-Things":[77],"industry,":[78],"it":[79],"is":[80],"timely":[81],"investigate":[83],"functionalities":[85],"limitations":[87],"memcomputing":[90],"structures,":[91],"such":[92],"as":[93],"those":[94],"arranged":[95],"cellular":[97],"bio-inspired":[98],"architectures.":[99],"adoption":[101],"memristors":[103],"circuit":[105],"design":[106,152],"brings":[107],"new":[108],"life":[109],"nonlinear":[111,147],"system":[112,122,148],"theory,":[113],"since":[114],"standard":[115,142],"analysis":[116],"synthesis":[118],"techniques":[119],"from":[120,146],"linear":[121],"theory":[123,149],"are":[124],"no":[125],"longer":[126],"applicable":[127],"for":[128,158,186],"investigation":[130],"highly-nonlinear":[132],"electronic":[133],"systems.":[134],"paper":[136],"demonstrates":[137],"how":[138],"use":[140],"novel":[144],"concepts":[145],"allow":[150],"Memristor":[154],"Cellular":[155],"Nonlinear":[156],"Network":[157],"execution":[160],"pixel-wise":[162],"logical":[163],"boolean":[164],"functions":[165],"binary":[167],"images,":[168],"concurrent":[171],"storage":[172],"input":[174],"or":[175],"output":[176],"into":[178],"memory":[181],"bank,":[182],"providing":[183],"clear":[184],"evidence":[185],"truly":[188],"character":[190],"its":[192],"memristor-centered":[193],"signal":[194],"processing":[195],"paradigm.":[196]},"counts_by_year":[{"year":2022,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}