{"id":"https://openalex.org/W2770141342","doi":"https://doi.org/10.1109/ecctd.2017.8093356","title":"VHDL implementation of FWL RLS algorithm","display_name":"VHDL implementation of FWL RLS algorithm","publication_year":2017,"publication_date":"2017-09-01","ids":{"openalex":"https://openalex.org/W2770141342","doi":"https://doi.org/10.1109/ecctd.2017.8093356","mag":"2770141342"},"language":"en","primary_location":{"id":"doi:10.1109/ecctd.2017.8093356","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2017.8093356","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 European Conference on Circuit Theory and Design (ECCTD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090882290","display_name":"Davide Bellizia","orcid":"https://orcid.org/0000-0002-6947-4410"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Davide Bellizia","raw_affiliation_strings":["Department of Information, University of Rome Sapinza, Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Information, University of Rome Sapinza, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070430111","display_name":"Pietro Monsurr\u00f2","orcid":"https://orcid.org/0000-0002-3821-6566"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Pietro Monsurro","raw_affiliation_strings":["Department of Information, University of Rome Sapinza, Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Information, University of Rome Sapinza, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068452963","display_name":"Alessandro Trifiletti","orcid":"https://orcid.org/0000-0001-6231-4273"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Alessandro Trifiletti","raw_affiliation_strings":["Department of Information, University of Rome Sapinza, Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Information, University of Rome Sapinza, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.247,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.57578149,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11233","display_name":"Advanced Adaptive Filtering Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2206","display_name":"Computational Mechanics"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11233","display_name":"Advanced Adaptive Filtering Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2206","display_name":"Computational Mechanics"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7212027311325073},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.6253601312637329},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5927641987800598},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5560968518257141},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.530770480632782},{"id":"https://openalex.org/keywords/recursive-least-squares-filter","display_name":"Recursive least squares filter","score":0.45833805203437805},{"id":"https://openalex.org/keywords/scalar","display_name":"Scalar (mathematics)","score":0.41989579796791077},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.30681782960891724},{"id":"https://openalex.org/keywords/adaptive-filter","display_name":"Adaptive filter","score":0.2837575674057007},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.23638933897018433}],"concepts":[{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7212027311325073},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.6253601312637329},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5927641987800598},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5560968518257141},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.530770480632782},{"id":"https://openalex.org/C145249878","wikidata":"https://www.wikidata.org/wiki/Q2835868","display_name":"Recursive least squares filter","level":3,"score":0.45833805203437805},{"id":"https://openalex.org/C57691317","wikidata":"https://www.wikidata.org/wiki/Q1289248","display_name":"Scalar (mathematics)","level":2,"score":0.41989579796791077},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.30681782960891724},{"id":"https://openalex.org/C102248274","wikidata":"https://www.wikidata.org/wiki/Q168388","display_name":"Adaptive filter","level":2,"score":0.2837575674057007},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.23638933897018433},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/ecctd.2017.8093356","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2017.8093356","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 European Conference on Circuit Theory and Design (ECCTD)","raw_type":"proceedings-article"},{"id":"pmh:oai:iris.uniroma1.it:11573/1026453","is_oa":false,"landing_page_url":"http://ieeexplore.ieee.org/document/8093356/","pdf_url":null,"source":{"id":"https://openalex.org/S4377196107","display_name":"IRIS Research product catalog (Sapienza University of Rome)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1506809288","https://openalex.org/W1632276823","https://openalex.org/W1650765400","https://openalex.org/W1998442795","https://openalex.org/W2372888562","https://openalex.org/W2521347584"],"related_works":["https://openalex.org/W3004362061","https://openalex.org/W4297665406","https://openalex.org/W2364622490","https://openalex.org/W2042515040","https://openalex.org/W2383986884","https://openalex.org/W2356141508","https://openalex.org/W2544043553","https://openalex.org/W1735031787","https://openalex.org/W2749962643","https://openalex.org/W2390807153"],"abstract_inverted_index":{"The":[0,39,125,189],"Frisch-Waugh-Lovell":[1],"(FWL)":[2],"Recursive":[3],"Least":[4],"Squares":[5],"(RLS)":[6],"algorithm":[7,15,42],"has":[8,30,43,116],"been":[9,31],"recently":[10],"proposed":[11],"as":[12,61],"an":[13,73,167],"RLS":[14,41,64,96,155],"with":[16,98],"lower":[17],"computational":[18],"cost":[19],"and":[20,86,106,120,144,161,174,194],"better":[21],"numerical":[22],"properties.":[23],"We":[24,204],"propose":[25],"a":[26,35,44,132,153,211],"VHDL":[27,190],"implementation":[28,126],"that":[29],"successfully":[32],"implemented":[33],"on":[34,129],"Xilinx":[36],"Virtex-7":[37],"FPGA.":[38],"FWL":[40],"complexity":[45],"of":[46,55,103,185,202,214],"L":[47,74,79,99,104,121,145,159,175,215],"<sup":[48,57],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[49,58],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[50,59],"+":[51,122,146,163,176],"O(L)":[52,60],"products,":[53],"instead":[54],"1.5L":[56],"in":[62,89],"conventional":[63,93],"algorithms.":[65],"Because":[66],"it":[67,83],"removes":[68],"all":[69],"matrix":[70],"operations,":[71],"separating":[72],"input":[75,168,181],"vector":[76],"problem":[77],"into":[78],"separate":[80],"scalar":[81,133],"problems,":[82],"is":[84,101,127,138,192],"stable":[85],"often":[87],"faster":[88],"fixed-point":[90],"arithmetic":[91],"than":[92],"RLS.":[94],"An":[95],"filter":[97],"inputs":[100,119],"composed":[102],"stages,":[105],"the":[107,183,186],"i-th":[108],"stage":[109],"(1":[110],"=":[111],"{1,":[112],"2,":[113],"...,":[114],"L})":[115],"L+":[117],"2-i":[118],"l-i":[123,147],"outputs.":[124],"based":[128],"two":[130],"blocks:":[131],"estimation":[134],"block":[135],"(EB),":[136],"which":[137],"instantiated":[139],"once":[140],"for":[141,199],"every":[142],"layer,":[143],"identical":[148],"filtering":[149],"blocks":[150],"(FB).":[151],"For":[152],"L-input":[154],"model,":[156],"there":[157],"are":[158],"EBs":[160],"L(L":[162],"l)/2":[164],"FBs.":[165,178],"Adding":[166],"involves":[169],"instantiating":[170],"one":[171,180],"additional":[172],"EB":[173],"1":[177],"Removing":[179],"requires":[182],"removal":[184],"first":[187],"layer.":[188],"structure":[191],"modular":[193],"can":[195],"be":[196],"easily":[197],"adjusted":[198],"different":[200],"values":[201],"L.":[203],"also":[205],"present":[206],"estimated":[207],"hardware":[208],"costs":[209],"over":[210],"wide":[212],"range":[213],"values.":[216]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
