{"id":"https://openalex.org/W2768607109","doi":"https://doi.org/10.1109/ecctd.2017.8093232","title":"Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology","display_name":"Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology","publication_year":2017,"publication_date":"2017-09-01","ids":{"openalex":"https://openalex.org/W2768607109","doi":"https://doi.org/10.1109/ecctd.2017.8093232","mag":"2768607109"},"language":"en","primary_location":{"id":"doi:10.1109/ecctd.2017.8093232","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2017.8093232","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 European Conference on Circuit Theory and Design (ECCTD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089445182","display_name":"Marten Vohrmann","orcid":"https://orcid.org/0000-0002-1202-7265"},"institutions":[{"id":"https://openalex.org/I20121455","display_name":"Bielefeld University","ror":"https://ror.org/02hpadn98","country_code":"DE","type":"education","lineage":["https://openalex.org/I20121455"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Marten Vohrmann","raw_affiliation_strings":["Universitat Bielefeld, Bielefeld, Nordrhein-Westfalen, DE"],"affiliations":[{"raw_affiliation_string":"Universitat Bielefeld, Bielefeld, Nordrhein-Westfalen, DE","institution_ids":["https://openalex.org/I20121455"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040365220","display_name":"Philippe Geisler","orcid":null},"institutions":[{"id":"https://openalex.org/I20121455","display_name":"Bielefeld University","ror":"https://ror.org/02hpadn98","country_code":"DE","type":"education","lineage":["https://openalex.org/I20121455"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Philippe Geisler","raw_affiliation_strings":["Cognitronics and Sensor Systems Group CITEC, Bielefeld University, Bielefeld, Germany"],"affiliations":[{"raw_affiliation_string":"Cognitronics and Sensor Systems Group CITEC, Bielefeld University, Bielefeld, Germany","institution_ids":["https://openalex.org/I20121455"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016691715","display_name":"Thorsten Jungeblut","orcid":"https://orcid.org/0000-0001-7425-8766"},"institutions":[{"id":"https://openalex.org/I20121455","display_name":"Bielefeld University","ror":"https://ror.org/02hpadn98","country_code":"DE","type":"education","lineage":["https://openalex.org/I20121455"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Thorsten Jungeblut","raw_affiliation_strings":["Cognitronics and Sensor Systems Group CITEC, Bielefeld University, Bielefeld, Germany"],"affiliations":[{"raw_affiliation_string":"Cognitronics and Sensor Systems Group CITEC, Bielefeld University, Bielefeld, Germany","institution_ids":["https://openalex.org/I20121455"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043372144","display_name":"Ulrich R\u00fcckert","orcid":null},"institutions":[{"id":"https://openalex.org/I20121455","display_name":"Bielefeld University","ror":"https://ror.org/02hpadn98","country_code":"DE","type":"education","lineage":["https://openalex.org/I20121455"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Ulrich Ruckert","raw_affiliation_strings":["Cognitronics and Sensor Systems Group CITEC, Bielefeld University, Bielefeld, Germany"],"affiliations":[{"raw_affiliation_string":"Cognitronics and Sensor Systems Group CITEC, Bielefeld University, Bielefeld, Germany","institution_ids":["https://openalex.org/I20121455"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5089445182"],"corresponding_institution_ids":["https://openalex.org/I20121455"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.15333824,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.7262275218963623},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.7210811972618103},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7132865190505981},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6526312828063965},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.636642336845398},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.6088727712631226},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5966309905052185},{"id":"https://openalex.org/keywords/transmission-gate","display_name":"Transmission gate","score":0.5515649914741516},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.5374166965484619},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5093604326248169},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5043128728866577},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.47344303131103516},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.4486364722251892},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.44022059440612793},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.4238671660423279},{"id":"https://openalex.org/keywords/silicon-on-insulator","display_name":"Silicon on insulator","score":0.41298577189445496},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4053402245044708},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3975491523742676},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.38963228464126587},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.304113507270813},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.22668415307998657},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.21361050009727478},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.19601893424987793},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.18514204025268555},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.16837313771247864},{"id":"https://openalex.org/keywords/silicon","display_name":"Silicon","score":0.07797104120254517}],"concepts":[{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.7262275218963623},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.7210811972618103},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7132865190505981},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6526312828063965},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.636642336845398},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.6088727712631226},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5966309905052185},{"id":"https://openalex.org/C2780949067","wikidata":"https://www.wikidata.org/wiki/Q1136752","display_name":"Transmission gate","level":4,"score":0.5515649914741516},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.5374166965484619},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5093604326248169},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5043128728866577},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.47344303131103516},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.4486364722251892},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.44022059440612793},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.4238671660423279},{"id":"https://openalex.org/C53143962","wikidata":"https://www.wikidata.org/wiki/Q1478788","display_name":"Silicon on insulator","level":3,"score":0.41298577189445496},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4053402245044708},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3975491523742676},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.38963228464126587},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.304113507270813},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.22668415307998657},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.21361050009727478},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.19601893424987793},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.18514204025268555},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.16837313771247864},{"id":"https://openalex.org/C544956773","wikidata":"https://www.wikidata.org/wiki/Q670","display_name":"Silicon","level":2,"score":0.07797104120254517},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/ecctd.2017.8093232","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2017.8093232","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 European Conference on Circuit Theory and Design (ECCTD)","raw_type":"proceedings-article"},{"id":"pmh:oai:pub.librecat.org:2918609","is_oa":false,"landing_page_url":"https://pub.uni-bielefeld.de/record/2918609","pdf_url":null,"source":{"id":"https://openalex.org/S4306401671","display_name":"PUB \u2013 Publications at Bielefeld University (Bielefeld University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I20121455","host_organization_name":"Bielefeld University","host_organization_lineage":["https://openalex.org/I20121455"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Vohrmann M, Geisler P, Jungeblut T, Ruckert U. Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology. In:  &lt;em&gt;2017 European Conference on Circuit Theory and Design (ECCTD)&lt;/em&gt;. IEEE;  2017.","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8999999761581421,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W649475307","https://openalex.org/W1575974143","https://openalex.org/W1933280719","https://openalex.org/W2055857026","https://openalex.org/W2088481695","https://openalex.org/W2106334424","https://openalex.org/W2166936511","https://openalex.org/W2167159964","https://openalex.org/W2994964425","https://openalex.org/W4285719527","https://openalex.org/W6771627385"],"related_works":["https://openalex.org/W2789662562","https://openalex.org/W4214735176","https://openalex.org/W2601542976","https://openalex.org/W2184476805","https://openalex.org/W2151687972","https://openalex.org/W2774143721","https://openalex.org/W3166523576","https://openalex.org/W2397249064","https://openalex.org/W2101829379","https://openalex.org/W4390551459"],"abstract_inverted_index":{"Logic":[0],"gates":[1,32,49,99,108,112],"for":[2,24,33,74],"ultra-low":[3],"voltages":[4],"suffer":[5],"from":[6],"speed":[7],"and":[8,47,109,119],"robustness":[9],"degradations,":[10],"which":[11],"are":[12],"highly":[13],"associated":[14],"with":[15,64],"the":[16,25,51,75,100],"process":[17],"technology.":[18],"In":[19],"this":[20],"work":[21],"a":[22,34,65],"methodology":[23],"automated":[26],"design-space":[27],"exploration":[28],"of":[29,45,53,61,69,79,115],"standard":[30,101],"logic":[31],"28":[35],"nm":[36],"FD-SOI":[37],"technology":[38],"is":[39,82,92],"shown.":[40],"Comprehensive":[41],"design":[42],"space":[43],"explorations":[44],"inverter":[46,76],"nand2":[48,98],"show":[50],"benefits":[52],"back-biasing":[54],"at":[55],"sub-threshold":[56],"supply":[57],"voltages.":[58],"A":[59],"comparison":[60],"Pareto":[62],"points":[63],"common":[66],"energy":[67],"consumption":[68],"1":[70],"fJ":[71],"shows":[72],"that":[73],"minimum":[77],"variation":[78,116],"3.66":[80],"%":[81],"achieved":[83],"utilizing":[84],"4":[85],"stacking":[86],"transistors":[87],"(LVT":[88,104],"type),":[89],"while":[90],"delay":[91,120],"increased":[93],"by":[94],"21":[95],"%.":[96],"For":[97],"CMOS":[102],"implementations":[103],"type)":[105],"outperforms":[106],"transmission":[107,111],"stacked":[110],"in":[113],"terms":[114],"(3.84":[117],"%)":[118],"(2.99":[121],"ns).":[122]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
