{"id":"https://openalex.org/W1927019565","doi":"https://doi.org/10.1109/ecctd.2015.7300008","title":"Power-efficient time-to-digital converter for all-digital frequency locked loops","display_name":"Power-efficient time-to-digital converter for all-digital frequency locked loops","publication_year":2015,"publication_date":"2015-08-01","ids":{"openalex":"https://openalex.org/W1927019565","doi":"https://doi.org/10.1109/ecctd.2015.7300008","mag":"1927019565"},"language":"en","primary_location":{"id":"doi:10.1109/ecctd.2015.7300008","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2015.7300008","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 European Conference on Circuit Theory and Design (ECCTD)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068305222","display_name":"Muhammad Touqir Pasha","orcid":"https://orcid.org/0000-0002-0624-0975"},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Muhammad Touqir Pasha","raw_affiliation_strings":["Department of Electrical Engineering, Link\u00f6ping University, Sweden","Dept. of Electrical Engineering, Link\u00f6ping University, Sweden"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Link\u00f6ping University, Sweden","institution_ids":["https://openalex.org/I102134673"]},{"raw_affiliation_string":"Dept. of Electrical Engineering, Link\u00f6ping University, Sweden","institution_ids":["https://openalex.org/I102134673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079301107","display_name":"Niklas Andersson","orcid":"https://orcid.org/0000-0002-6032-5494"},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Niklas U. Andersson","raw_affiliation_strings":["Department of Electrical Engineering, Link\u00f6ping University, Sweden","Dept. of Electrical Engineering, Link\u00f6ping University, Sweden"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Link\u00f6ping University, Sweden","institution_ids":["https://openalex.org/I102134673"]},{"raw_affiliation_string":"Dept. of Electrical Engineering, Link\u00f6ping University, Sweden","institution_ids":["https://openalex.org/I102134673"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5047505166","display_name":"Mark Vesterbacka","orcid":null},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Mark Vesterbacka","raw_affiliation_strings":["Department of Electrical Engineering, Link\u00f6ping University, Sweden","Dept. of Electrical Engineering, Link\u00f6ping University, Sweden"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Link\u00f6ping University, Sweden","institution_ids":["https://openalex.org/I102134673"]},{"raw_affiliation_string":"Dept. of Electrical Engineering, Link\u00f6ping University, Sweden","institution_ids":["https://openalex.org/I102134673"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I102134673"],"apc_list":null,"apc_paid":null,"fwci":0.4118,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.51228771,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vernier-scale","display_name":"Vernier scale","score":0.7790244817733765},{"id":"https://openalex.org/keywords/time-to-digital-converter","display_name":"Time-to-digital converter","score":0.6558676362037659},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6038912534713745},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.585045337677002},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.5786823034286499},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.557792603969574},{"id":"https://openalex.org/keywords/dynamic-range","display_name":"Dynamic range","score":0.4685210883617401},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.42145371437072754},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.4192749857902527},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.41159260272979736},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.4009305238723755},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33137983083724976},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.30870574712753296},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.27635934948921204},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22683295607566833},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.22097384929656982},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.15347471833229065},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.10886767506599426}],"concepts":[{"id":"https://openalex.org/C69710193","wikidata":"https://www.wikidata.org/wiki/Q14946576","display_name":"Vernier scale","level":2,"score":0.7790244817733765},{"id":"https://openalex.org/C99594498","wikidata":"https://www.wikidata.org/wiki/Q2434524","display_name":"Time-to-digital converter","level":4,"score":0.6558676362037659},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6038912534713745},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.585045337677002},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5786823034286499},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.557792603969574},{"id":"https://openalex.org/C87133666","wikidata":"https://www.wikidata.org/wiki/Q1161699","display_name":"Dynamic range","level":2,"score":0.4685210883617401},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.42145371437072754},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.4192749857902527},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.41159260272979736},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.4009305238723755},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33137983083724976},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.30870574712753296},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.27635934948921204},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22683295607566833},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.22097384929656982},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.15347471833229065},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.10886767506599426},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C1276947","wikidata":"https://www.wikidata.org/wiki/Q333","display_name":"Astronomy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ecctd.2015.7300008","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2015.7300008","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 European Conference on Circuit Theory and Design (ECCTD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8899999856948853,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W152792319","https://openalex.org/W654799228","https://openalex.org/W1603675831","https://openalex.org/W1972578932","https://openalex.org/W2006777860","https://openalex.org/W2069310970","https://openalex.org/W2112856903","https://openalex.org/W2128282260","https://openalex.org/W2149726555","https://openalex.org/W2166155244","https://openalex.org/W2171297533"],"related_works":["https://openalex.org/W3158414702","https://openalex.org/W4389545333","https://openalex.org/W2296652335","https://openalex.org/W2182982459","https://openalex.org/W2112856903","https://openalex.org/W2541226935","https://openalex.org/W2120912680","https://openalex.org/W1984418134","https://openalex.org/W3022509112","https://openalex.org/W2547517791"],"abstract_inverted_index":{"An":[0],"8-bit":[1],"time-to-digital":[2],"converter":[3],"(TDC)":[4],"for":[5,39],"all-digital":[6],"frequency-locked":[7],"loops":[8],"is":[9,53,85],"presented.":[10],"The":[11,47,82],"selected":[12],"architecture":[13,37],"uses":[14],"a":[15,28,57,68,89],"Vernier":[16],"delay":[17,34],"line":[18],"where":[19],"the":[20,33,51],"commonly":[21],"used":[22],"D":[23],"flip-flops":[24],"are":[25],"replaced":[26],"with":[27,73,88],"single":[29],"enable":[30],"transistor":[31],"in":[32,67],"elements.":[35],"This":[36],"allows":[38],"an":[40,74],"area":[41,77],"efficient":[42,45],"and":[43],"power":[44,90],"implementation.":[46],"dynamic":[48],"range":[49],"of":[50,78,92],"TDC":[52],"extended":[54],"by":[55],"using":[56],"6-bit":[58],"gray":[59],"counter.":[60],"A":[61],"prototype":[62],"chip":[63],"has":[64],"been":[65],"implemented":[66],"65":[69],"nm":[70],"CMOS":[71],"process":[72],"active":[75],"core":[76],"75\u03bcm":[79],"\u00d7":[80],"120\u03bcm.":[81],"time":[83],"resolution":[84],"5.7":[86],"ps":[87],"consumption":[91],"1.85":[93],"mW":[94],"measured":[95],"at":[96],"50":[97],"MHz":[98],"sampling":[99],"frequency.":[100]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
