{"id":"https://openalex.org/W1974756536","doi":"https://doi.org/10.1109/ecctd.2013.6662284","title":"Reliable and efficient phase noise simulation of mixed-mode integer-N Phase-Locked Loops","display_name":"Reliable and efficient phase noise simulation of mixed-mode integer-N Phase-Locked Loops","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W1974756536","doi":"https://doi.org/10.1109/ecctd.2013.6662284","mag":"1974756536"},"language":"en","primary_location":{"id":"doi:10.1109/ecctd.2013.6662284","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2013.6662284","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 European Conference on Circuit Theory and Design (ECCTD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5045065266","display_name":"M. Biggio","orcid":null},"institutions":[{"id":"https://openalex.org/I83816512","display_name":"University of Genoa","ror":"https://ror.org/0107c5v14","country_code":"IT","type":"education","lineage":["https://openalex.org/I83816512"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Matteo Biggio","raw_affiliation_strings":["DITEN, University of Genoa, Genova, Italy","DITEN, University of Genoa, Genoa, Italy#TAB#"],"affiliations":[{"raw_affiliation_string":"DITEN, University of Genoa, Genova, Italy","institution_ids":["https://openalex.org/I83816512"]},{"raw_affiliation_string":"DITEN, University of Genoa, Genoa, Italy#TAB#","institution_ids":["https://openalex.org/I83816512"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086093589","display_name":"Federico Bizzarri","orcid":"https://orcid.org/0000-0002-6568-6491"},"institutions":[{"id":"https://openalex.org/I4210142020","display_name":"Consorzio di Bioingegneria e Informatica Medica","ror":"https://ror.org/044w95594","country_code":"IT","type":"other","lineage":["https://openalex.org/I4210142020"]},{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Federico Bizzarri","raw_affiliation_strings":["Dipartimento di Elettronica, Informazione e Bioingegneria, Milano, Italy","Dipt. di Elettron., Inf. e Bioingegneria, Politec. di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Informazione e Bioingegneria, Milano, Italy","institution_ids":["https://openalex.org/I4210142020"]},{"raw_affiliation_string":"Dipt. di Elettron., Inf. e Bioingegneria, Politec. di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080022239","display_name":"Angelo Brambilla","orcid":"https://orcid.org/0000-0001-9422-6446"},"institutions":[{"id":"https://openalex.org/I4210142020","display_name":"Consorzio di Bioingegneria e Informatica Medica","ror":"https://ror.org/044w95594","country_code":"IT","type":"other","lineage":["https://openalex.org/I4210142020"]},{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Angelo Brambilla","raw_affiliation_strings":["Dipartimento di Elettronica, Informazione e Bioingegneria, Milano, Italy","Dipt. di Elettron., Inf. e Bioingegneria, Politec. di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Informazione e Bioingegneria, Milano, Italy","institution_ids":["https://openalex.org/I4210142020"]},{"raw_affiliation_string":"Dipt. di Elettron., Inf. e Bioingegneria, Politec. di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064340327","display_name":"Giorgio Carlini","orcid":null},"institutions":[{"id":"https://openalex.org/I83816512","display_name":"University of Genoa","ror":"https://ror.org/0107c5v14","country_code":"IT","type":"education","lineage":["https://openalex.org/I83816512"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Giorgio Carlini","raw_affiliation_strings":["DITEN, University of Genoa, Genova, Italy","DITEN, University of Genoa, Genoa, Italy#TAB#"],"affiliations":[{"raw_affiliation_string":"DITEN, University of Genoa, Genova, Italy","institution_ids":["https://openalex.org/I83816512"]},{"raw_affiliation_string":"DITEN, University of Genoa, Genoa, Italy#TAB#","institution_ids":["https://openalex.org/I83816512"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5042093020","display_name":"Marco Storace","orcid":"https://orcid.org/0000-0003-4958-074X"},"institutions":[{"id":"https://openalex.org/I83816512","display_name":"University of Genoa","ror":"https://ror.org/0107c5v14","country_code":"IT","type":"education","lineage":["https://openalex.org/I83816512"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Marco Storace","raw_affiliation_strings":["DITEN, University of Genoa, Genova, Italy","DITEN, University of Genoa, Genoa, Italy#TAB#"],"affiliations":[{"raw_affiliation_string":"DITEN, University of Genoa, Genova, Italy","institution_ids":["https://openalex.org/I83816512"]},{"raw_affiliation_string":"DITEN, University of Genoa, Genoa, Italy#TAB#","institution_ids":["https://openalex.org/I83816512"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5045065266"],"corresponding_institution_ids":["https://openalex.org/I83816512"],"apc_list":null,"apc_paid":null,"fwci":1.2012,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.80699581,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.6787521243095398},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.6234678030014038},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6061672568321228},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.603708028793335},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5212819576263428},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5087798237800598},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.4708271324634552},{"id":"https://openalex.org/keywords/integer","display_name":"Integer (computer science)","score":0.4283676743507385},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.369278222322464},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2277149260044098},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.15380576252937317},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.1121549904346466}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.6787521243095398},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.6234678030014038},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6061672568321228},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.603708028793335},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5212819576263428},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5087798237800598},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.4708271324634552},{"id":"https://openalex.org/C97137487","wikidata":"https://www.wikidata.org/wiki/Q729138","display_name":"Integer (computer science)","level":2,"score":0.4283676743507385},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.369278222322464},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2277149260044098},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.15380576252937317},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.1121549904346466},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/ecctd.2013.6662284","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2013.6662284","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 European Conference on Circuit Theory and Design (ECCTD)","raw_type":"proceedings-article"},{"id":"pmh:oai:iris.unige.it:11567/695369","is_oa":false,"landing_page_url":"https://hdl.handle.net/11567/695369","pdf_url":null,"source":{"id":"https://openalex.org/S4377196291","display_name":"CINECA IRIS Institutial Research Information System (University of Genoa)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I83816512","host_organization_name":"University of Genoa","host_organization_lineage":["https://openalex.org/I83816512"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:re.public.polimi.it:11311/868393","is_oa":false,"landing_page_url":"http://hdl.handle.net/11311/868393","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320326078","display_name":"Regione Lombardia","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1552277675","https://openalex.org/W1904904019","https://openalex.org/W1908606840","https://openalex.org/W1970347687","https://openalex.org/W1998369000","https://openalex.org/W2052773149","https://openalex.org/W2072558413","https://openalex.org/W2080673725","https://openalex.org/W2086848907","https://openalex.org/W2115477597","https://openalex.org/W2140153041","https://openalex.org/W2141960683","https://openalex.org/W2150374644","https://openalex.org/W2319973481","https://openalex.org/W4232610995"],"related_works":["https://openalex.org/W1576949837","https://openalex.org/W4360861688","https://openalex.org/W3134930219","https://openalex.org/W2474043983","https://openalex.org/W2078513307","https://openalex.org/W2566880546","https://openalex.org/W2544336511","https://openalex.org/W2144737022","https://openalex.org/W2000633969","https://openalex.org/W1978186604"],"abstract_inverted_index":{"In":[0],"this":[1,35,65],"paper":[2],"the":[3,8,49,54,79,82,89],"results":[4,76],"obtained":[5],"by":[6,41],"performing":[7],"Periodic":[9],"Noise":[10],"(PNoise)":[11],"analysis":[12,33,91],"of":[13,34,37,67,81,88,95],"a":[14,20,106],"Phase-Locked":[15],"Loop":[16],"(pll)":[17],"modeled":[18],"as":[19,44],"mixed":[21],"analog/digital":[22],"circuit":[23,50],"are":[24,59],"compared":[25],"with":[26,105],"those":[27],"from":[28],"experimental":[29,69],"measurements.":[30],"The":[31],"PNoise":[32,90],"class":[36],"circuits":[38],"is":[39,71,110],"done":[40],"considering":[42],"them":[43],"hybrid":[45],"dynamical":[46],"systems.":[47],"Since":[48],"simulators":[51],"available":[52],"on":[53],"academic":[55],"and":[56,77],"industrial":[57],"shelves":[58],"not":[60],"able":[61],"to":[62,73,115],"carry":[63],"out":[64],"kind":[66],"simulation,":[68],"validation":[70],"mandatory":[72],"support":[74],"numerical":[75],"enforce":[78],"reliability":[80],"proposed":[83],"approach.":[84],"A":[85],"significant":[86],"improvement":[87],"efficiency,":[92],"in":[93,103],"terms":[94],"reducing":[96],"its":[97],"computational":[98],"burden":[99],"when":[100],"simulating":[101],"noise":[102,119],"PLLs":[104],"large":[107],"frequency":[108],"ratio,":[109],"also":[111],"presented,":[112],"which":[113],"allows":[114],"more":[116],"easily":[117],"manage":[118],"folding.":[120]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
