{"id":"https://openalex.org/W1974351049","doi":"https://doi.org/10.1109/ecctd.2013.6662198","title":"Experimental validation of DAC with nested bus-splitting EFM4 DDSM","display_name":"Experimental validation of DAC with nested bus-splitting EFM4 DDSM","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W1974351049","doi":"https://doi.org/10.1109/ecctd.2013.6662198","mag":"1974351049"},"language":"en","primary_location":{"id":"doi:10.1109/ecctd.2013.6662198","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2013.6662198","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 European Conference on Circuit Theory and Design (ECCTD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068806003","display_name":"Hongjia Mo","orcid":"https://orcid.org/0000-0002-0310-445X"},"institutions":[{"id":"https://openalex.org/I27577105","display_name":"University College Cork","ror":"https://ror.org/03265fv13","country_code":"IE","type":"education","lineage":["https://openalex.org/I27577105"]},{"id":"https://openalex.org/I181231927","display_name":"National University of Ireland","ror":"https://ror.org/00shsf120","country_code":"IE","type":"education","lineage":["https://openalex.org/I181231927"]}],"countries":["IE"],"is_corresponding":true,"raw_author_name":"Hongjia Mo","raw_affiliation_strings":["Department of Electrical & Electronic Engineering, University College Cork and Tyndall National Institute, Cork, Ireland","[Dept. of Electr. & Electron. Eng., Univ. Coll. Cork, Cork, Ireland]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical & Electronic Engineering, University College Cork and Tyndall National Institute, Cork, Ireland","institution_ids":["https://openalex.org/I181231927","https://openalex.org/I27577105"]},{"raw_affiliation_string":"[Dept. of Electr. & Electron. Eng., Univ. Coll. Cork, Cork, Ireland]","institution_ids":["https://openalex.org/I27577105"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058028927","display_name":"Michael Peter Kennedy","orcid":"https://orcid.org/0000-0003-3242-1056"},"institutions":[{"id":"https://openalex.org/I181231927","display_name":"National University of Ireland","ror":"https://ror.org/00shsf120","country_code":"IE","type":"education","lineage":["https://openalex.org/I181231927"]},{"id":"https://openalex.org/I27577105","display_name":"University College Cork","ror":"https://ror.org/03265fv13","country_code":"IE","type":"education","lineage":["https://openalex.org/I27577105"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Michael Peter Kennedy","raw_affiliation_strings":["Department of Electrical & Electronic Engineering, University College Cork and Tyndall National Institute, Cork, Ireland","[Dept. of Electr. & Electron. Eng., Univ. Coll. Cork, Cork, Ireland]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical & Electronic Engineering, University College Cork and Tyndall National Institute, Cork, Ireland","institution_ids":["https://openalex.org/I181231927","https://openalex.org/I27577105"]},{"raw_affiliation_string":"[Dept. of Electr. & Electron. Eng., Univ. Coll. Cork, Cork, Ireland]","institution_ids":["https://openalex.org/I27577105"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009357679","display_name":"Vincent O\u2019Brien","orcid":"https://orcid.org/0000-0002-8209-6661"},"institutions":[{"id":"https://openalex.org/I230495080","display_name":"University of Limerick","ror":"https://ror.org/00a0n9e72","country_code":"IE","type":"education","lineage":["https://openalex.org/I230495080"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Vincent O'Brien","raw_affiliation_strings":["Circuits and Systems Research Centre, University of Limerick, Limerick, Ireland","[Circuits and Systems Research Centre, University of Limerick, Limerick, Ireland]"],"affiliations":[{"raw_affiliation_string":"Circuits and Systems Research Centre, University of Limerick, Limerick, Ireland","institution_ids":["https://openalex.org/I230495080"]},{"raw_affiliation_string":"[Circuits and Systems Research Centre, University of Limerick, Limerick, Ireland]","institution_ids":["https://openalex.org/I230495080"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037035551","display_name":"Brendan Mullane","orcid":"https://orcid.org/0000-0003-3764-3555"},"institutions":[{"id":"https://openalex.org/I230495080","display_name":"University of Limerick","ror":"https://ror.org/00a0n9e72","country_code":"IE","type":"education","lineage":["https://openalex.org/I230495080"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Brendan Mullane","raw_affiliation_strings":["Circuits and Systems Research Centre, University of Limerick, Limerick, Ireland","[Circuits and Systems Research Centre, University of Limerick, Limerick, Ireland]"],"affiliations":[{"raw_affiliation_string":"Circuits and Systems Research Centre, University of Limerick, Limerick, Ireland","institution_ids":["https://openalex.org/I230495080"]},{"raw_affiliation_string":"[Circuits and Systems Research Centre, University of Limerick, Limerick, Ireland]","institution_ids":["https://openalex.org/I230495080"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5068806003"],"corresponding_institution_ids":["https://openalex.org/I181231927","https://openalex.org/I27577105"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.05763509,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5871813893318176},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5844981670379639},{"id":"https://openalex.org/keywords/matching","display_name":"Matching (statistics)","score":0.5026018619537354},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.5022761821746826},{"id":"https://openalex.org/keywords/degradation","display_name":"Degradation (telecommunications)","score":0.49837827682495117},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.38483020663261414},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.28384923934936523},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19139614701271057},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11709752678871155},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0938442051410675}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5871813893318176},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5844981670379639},{"id":"https://openalex.org/C165064840","wikidata":"https://www.wikidata.org/wiki/Q1321061","display_name":"Matching (statistics)","level":2,"score":0.5026018619537354},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.5022761821746826},{"id":"https://openalex.org/C2779679103","wikidata":"https://www.wikidata.org/wiki/Q5251805","display_name":"Degradation (telecommunications)","level":2,"score":0.49837827682495117},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.38483020663261414},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.28384923934936523},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19139614701271057},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11709752678871155},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0938442051410675},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ecctd.2013.6662198","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2013.6662198","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 European Conference on Circuit Theory and Design (ECCTD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W605564925","https://openalex.org/W1566753641","https://openalex.org/W1985145788","https://openalex.org/W2001449089","https://openalex.org/W2004707075","https://openalex.org/W2075670660","https://openalex.org/W2109963032","https://openalex.org/W2140481264","https://openalex.org/W2149655780","https://openalex.org/W2157832315","https://openalex.org/W2586762050","https://openalex.org/W4301627548","https://openalex.org/W6669150735"],"related_works":["https://openalex.org/W2544043553","https://openalex.org/W2546284597","https://openalex.org/W2348562861","https://openalex.org/W2540393334","https://openalex.org/W1983570530","https://openalex.org/W2062932566","https://openalex.org/W2390042878","https://openalex.org/W2085828379","https://openalex.org/W2271847574","https://openalex.org/W2746234147"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"measured":[3],"results":[4],"for":[5],"a":[6,20,33,37],"fourth":[7],"order":[8],"nested":[9,24],"bus-splitting":[10,25],"Error":[11],"Feedback":[12],"Modulator":[13],"(EFM4)":[14],"with":[15,41],"dynamic":[16],"element":[17],"matching":[18],"and":[19],"four-bit":[21],"DAC.":[22],"The":[23],"EFM4":[26,35],"can":[27],"run":[28],"approximately":[29],"38%":[30],"faster":[31],"than":[32],"conventional":[34],"on":[36],"Xilinx":[38],"Virtex":[39],"5,":[40],"negligible":[42],"degradation":[43],"in":[44],"spectral":[45],"performance.":[46]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}