{"id":"https://openalex.org/W2148556461","doi":"https://doi.org/10.1109/ecctd.2011.6043824","title":"LDS - A description script for layout templates","display_name":"LDS - A description script for layout templates","publication_year":2011,"publication_date":"2011-08-01","ids":{"openalex":"https://openalex.org/W2148556461","doi":"https://doi.org/10.1109/ecctd.2011.6043824","mag":"2148556461"},"language":"en","primary_location":{"id":"doi:10.1109/ecctd.2011.6043824","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2011.6043824","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007224473","display_name":"Ahmet Unutulmaz","orcid":"https://orcid.org/0000-0001-7738-9286"},"institutions":[{"id":"https://openalex.org/I4405392","display_name":"Bo\u011fazi\u00e7i University","ror":"https://ror.org/03z9tma90","country_code":"TR","type":"education","lineage":["https://openalex.org/I4405392"]}],"countries":["TR"],"is_corresponding":false,"raw_author_name":"A. Unutulmaz","raw_affiliation_strings":["School of Electrical and Electronics Engineering, Bogazici University, Turkey"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronics Engineering, Bogazici University, Turkey","institution_ids":["https://openalex.org/I4405392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052669741","display_name":"G\u00fcnhan D\u00fcndar","orcid":"https://orcid.org/0000-0003-2044-2706"},"institutions":[{"id":"https://openalex.org/I4405392","display_name":"Bo\u011fazi\u00e7i University","ror":"https://ror.org/03z9tma90","country_code":"TR","type":"education","lineage":["https://openalex.org/I4405392"]}],"countries":["TR"],"is_corresponding":false,"raw_author_name":"G. Dundar","raw_affiliation_strings":["School of Electrical and Electronics Engineering, Bogazici University, Turkey"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronics Engineering, Bogazici University, Turkey","institution_ids":["https://openalex.org/I4405392"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041853563","display_name":"F.V. Fern\u00e1ndez","orcid":"https://orcid.org/0000-0001-8682-2280"},"institutions":[{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"F.V. Fernandez","raw_affiliation_strings":["IMSE-CNM, CSIC, University of Sevilla, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IMSE-CNM, CSIC, University of Sevilla, Spain","institution_ids":["https://openalex.org/I4210104545"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.685,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.90719026,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"857","last_page":"860"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/template","display_name":"Template","score":0.8176916837692261},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8161470890045166},{"id":"https://openalex.org/keywords/ic-layout-editor","display_name":"IC layout editor","score":0.6711921691894531},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.6169198155403137},{"id":"https://openalex.org/keywords/coding","display_name":"Coding (social sciences)","score":0.5550596117973328},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.5469191670417786},{"id":"https://openalex.org/keywords/design-layout-record","display_name":"Design layout record","score":0.5175061225891113},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5016818046569824},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.49446582794189453},{"id":"https://openalex.org/keywords/engineering-drawing","display_name":"Engineering drawing","score":0.40094292163848877},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.33299529552459717},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.32156676054000854},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.24646234512329102},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.17240822315216064},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09452739357948303},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07776838541030884}],"concepts":[{"id":"https://openalex.org/C82714645","wikidata":"https://www.wikidata.org/wiki/Q438331","display_name":"Template","level":2,"score":0.8176916837692261},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8161470890045166},{"id":"https://openalex.org/C5546195","wikidata":"https://www.wikidata.org/wiki/Q5969842","display_name":"IC layout editor","level":5,"score":0.6711921691894531},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.6169198155403137},{"id":"https://openalex.org/C179518139","wikidata":"https://www.wikidata.org/wiki/Q5140297","display_name":"Coding (social sciences)","level":2,"score":0.5550596117973328},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.5469191670417786},{"id":"https://openalex.org/C179145894","wikidata":"https://www.wikidata.org/wiki/Q5264353","display_name":"Design layout record","level":5,"score":0.5175061225891113},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5016818046569824},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.49446582794189453},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.40094292163848877},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.33299529552459717},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.32156676054000854},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.24646234512329102},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.17240822315216064},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09452739357948303},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07776838541030884},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/ecctd.2011.6043824","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2011.6043824","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","raw_type":"proceedings-article"},{"id":"pmh:oai:digital.csic.es:10261/83815","is_oa":false,"landing_page_url":"http://hdl.handle.net/10261/83815","pdf_url":null,"source":{"id":"https://openalex.org/S4306400616","display_name":"DIGITAL.CSIC (Spanish National Research Council (CSIC))","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I134820265","host_organization_name":"Consejo Superior de Investigaciones Cient\u00edficas","host_organization_lineage":["https://openalex.org/I134820265"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Comunicaci\u00f3n de congreso"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Quality Education","id":"https://metadata.un.org/sdg/4","score":0.6200000047683716}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W2110514755","https://openalex.org/W2116962939","https://openalex.org/W2116989584","https://openalex.org/W2144473140","https://openalex.org/W2149029467","https://openalex.org/W2151538019","https://openalex.org/W2162651506","https://openalex.org/W2169559614","https://openalex.org/W4236626993","https://openalex.org/W4236846038","https://openalex.org/W4238577093","https://openalex.org/W4240309467"],"related_works":["https://openalex.org/W2091329789","https://openalex.org/W2595178692","https://openalex.org/W1873584906","https://openalex.org/W2044122268","https://openalex.org/W1605062719","https://openalex.org/W2003092850","https://openalex.org/W2248366743","https://openalex.org/W2376028644","https://openalex.org/W2357425846","https://openalex.org/W2123992435"],"abstract_inverted_index":{"In":[0,21],"this":[1],"paper":[2],"a":[3,30,48,51,72,78,103,106],"simple":[4],"declarative":[5],"language":[6,88],"to":[7,23,46,57,74,101],"define":[8],"layout":[9,49,80,104],"templates":[10],"of":[11,29,53],"analog":[12],"circuits,":[13],"named":[14],"Layout":[15],"Description":[16],"Script":[17],"(LDS),":[18],"is":[19,32,44,66,81,99],"introduced.":[20],"contrast":[22],"sequential":[24],"description":[25,87],"languages,":[26],"coding":[27],"constraints":[28],"template":[31],"very":[33],"easy":[34],"with":[35],"LDS.":[36],"A":[37],"methodology":[38,73,98],"based":[39],"on":[40],"linear":[41],"programming":[42],"(LP)":[43],"presented":[45],"instantiate":[47],"from":[50,77],"set":[52],"LDS":[54,76],"statements.":[55],"Due":[56],"the":[58,86],"LP":[59],"formulation,":[60],"area":[61],"and":[62,85],"wire":[63],"length":[64],"minimization":[65],"also":[67],"applied":[68],"during":[69],"instantiation.":[70],"Also":[71],"extract":[75],"pre-drawn":[79],"presented.":[82],"These":[83],"methodologies":[84],"itself":[89],"are":[90],"illustrated":[91],"by":[92],"synthesizing":[93],"an":[94],"amplifier.":[95],"The":[96],"proposed":[97],"able":[100],"synthesize":[102],"in":[105],"few":[107],"seconds.":[108]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
