{"id":"https://openalex.org/W2136731522","doi":"https://doi.org/10.1109/ecctd.2011.6043609","title":"A fully automated large-scale addressable test chip design with high reliability","display_name":"A fully automated large-scale addressable test chip design with high reliability","publication_year":2011,"publication_date":"2011-08-01","ids":{"openalex":"https://openalex.org/W2136731522","doi":"https://doi.org/10.1109/ecctd.2011.6043609","mag":"2136731522"},"language":"en","primary_location":{"id":"doi:10.1109/ecctd.2011.6043609","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2011.6043609","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5114377942","display_name":"Bo Zhang","orcid":"https://orcid.org/0000-0002-0821-2361"},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Bo Zhang","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, China","Institute of VLSI Design Zhejiang University,Hangzhou 310027,China)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]},{"raw_affiliation_string":"Institute of VLSI Design Zhejiang University,Hangzhou 310027,China)","institution_ids":["https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5114910588","display_name":"Weiwei Pan","orcid":"https://orcid.org/0000-0001-8323-861X"},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Weiwei Pan","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, China","Institute of VLSI Design Zhejiang University,Hangzhou 310027,China)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]},{"raw_affiliation_string":"Institute of VLSI Design Zhejiang University,Hangzhou 310027,China)","institution_ids":["https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100717642","display_name":"Yongjun Zheng","orcid":"https://orcid.org/0000-0003-0824-2365"},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yongjun Zheng","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, China","Institute of VLSI Design Zhejiang University,Hangzhou 310027,China)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]},{"raw_affiliation_string":"Institute of VLSI Design Zhejiang University,Hangzhou 310027,China)","institution_ids":["https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100775131","display_name":"Zheng Shi","orcid":"https://orcid.org/0000-0003-4952-9389"},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zheng Shi","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, China","Institute of VLSI Design Zhejiang University,Hangzhou 310027,China)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]},{"raw_affiliation_string":"Institute of VLSI Design Zhejiang University,Hangzhou 310027,China)","institution_ids":["https://openalex.org/I76130692"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101586250","display_name":"Xiaolang Yan","orcid":"https://orcid.org/0000-0003-2284-3036"},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaolang Yan","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, China","Institute of VLSI Design Zhejiang University,Hangzhou 310027,China)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]},{"raw_affiliation_string":"Institute of VLSI Design Zhejiang University,Hangzhou 310027,China)","institution_ids":["https://openalex.org/I76130692"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.17051865,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"61","last_page":"64"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-for-manufacturability","display_name":"Design for manufacturability","score":0.8994308114051819},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.6484950184822083},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.6447471380233765},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6165968179702759},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.6053001880645752},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5284742116928101},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.4928584098815918},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.45019271969795227},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.4486999213695526},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25920695066452026},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.0932154655456543}],"concepts":[{"id":"https://openalex.org/C62064638","wikidata":"https://www.wikidata.org/wiki/Q553878","display_name":"Design for manufacturability","level":2,"score":0.8994308114051819},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.6484950184822083},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6447471380233765},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6165968179702759},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.6053001880645752},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5284742116928101},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.4928584098815918},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.45019271969795227},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.4486999213695526},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25920695066452026},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0932154655456543},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ecctd.2011.6043609","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2011.6043609","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Peace, Justice and strong institutions","id":"https://metadata.un.org/sdg/16","score":0.6299999952316284}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1830543919","https://openalex.org/W1990154543","https://openalex.org/W1995051012","https://openalex.org/W2059827991","https://openalex.org/W2093193587","https://openalex.org/W2102067969","https://openalex.org/W2126030992","https://openalex.org/W2139874673","https://openalex.org/W2148100777"],"related_works":["https://openalex.org/W2094969048","https://openalex.org/W994558755","https://openalex.org/W2010746423","https://openalex.org/W3035935536","https://openalex.org/W2117710422","https://openalex.org/W2372119205","https://openalex.org/W2078862364","https://openalex.org/W3214257365","https://openalex.org/W2489638043","https://openalex.org/W1827781850"],"abstract_inverted_index":{"During":[0],"the":[1,33,39,86,106,112],"development":[2,62],"of":[3,16,18,23,41,46,85,116],"modern":[4],"semiconductor":[5],"processes,":[6],"which":[7],"has":[8,98],"increasing":[9],"complexity":[10],"and":[11,31,35,74,82,101,114],"an":[12],"extremely":[13],"high":[14],"number":[15,22],"degrees":[17],"freedom,":[19],"a":[20,56,95],"large":[21],"distinct":[24],"test":[25,30,47,60,108],"structures":[26],"are":[27],"required":[28],"to":[29,76,80],"ensure":[32],"yield":[34],"manufacturability.":[36],"To":[37],"increase":[38],"utilization":[40],"chip":[42,48,61],"area,":[43],"addressable":[44,59],"methodology":[45],"is":[49,71],"developed.":[50],"In":[51],"this":[52,69,104,117],"paper,":[53],"we":[54],"present":[55],"novel":[57],"large-scale":[58],"procedure.":[63,118],"Based":[64],"on":[65,94],"components":[66],"for":[67,88],"automation,":[68],"procedure":[70],"fully":[72],"integrated":[73],"able":[75],"reduce":[77],"layout":[78],"time":[79],"10%":[81],"eliminate":[83],"much":[84],"potential":[87],"human":[89],"error.":[90],"A":[91],"32\u00d732":[92],"array":[93],"45nm":[96],"technology":[97],"been":[99],"designed":[100],"manufactured":[102],"with":[103],"procedure;":[105],"silicon":[107],"data":[109],"further":[110],"prove":[111],"reliability":[113],"effectiveness":[115]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2015,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
