{"id":"https://openalex.org/W2118629191","doi":"https://doi.org/10.1109/ecctd.2009.5275075","title":"A new power grid optimization algorithm based on manufacturing cost restriction","display_name":"A new power grid optimization algorithm based on manufacturing cost restriction","publication_year":2009,"publication_date":"2009-08-01","ids":{"openalex":"https://openalex.org/W2118629191","doi":"https://doi.org/10.1109/ecctd.2009.5275075","mag":"2118629191"},"language":"en","primary_location":{"id":"doi:10.1109/ecctd.2009.5275075","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2009.5275075","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 European Conference on Circuit Theory and Design","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5003899185","display_name":"Takayuki Hayashi","orcid":null},"institutions":[{"id":"https://openalex.org/I135768898","display_name":"Ritsumeikan University","ror":"https://ror.org/0197nmd03","country_code":"JP","type":"education","lineage":["https://openalex.org/I135768898","https://openalex.org/I4390039241"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Takayuki Hayashi","raw_affiliation_strings":["Department VLSI System Design, Ritsumeikan University, Kusatsu, Japan","Dept. VLSI System Design, Ritsumeikan University Kusatsu, 525-8577 Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department VLSI System Design, Ritsumeikan University, Kusatsu, Japan","institution_ids":["https://openalex.org/I135768898"]},{"raw_affiliation_string":"Dept. VLSI System Design, Ritsumeikan University Kusatsu, 525-8577 Japan","institution_ids":["https://openalex.org/I135768898"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048830310","display_name":"Masahiro Fukui","orcid":"https://orcid.org/0000-0001-6436-9040"},"institutions":[{"id":"https://openalex.org/I135768898","display_name":"Ritsumeikan University","ror":"https://ror.org/0197nmd03","country_code":"JP","type":"education","lineage":["https://openalex.org/I135768898","https://openalex.org/I4390039241"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahiro Fukui","raw_affiliation_strings":["Department VLSI System Design, Ritsumeikan University, Kusatsu, Japan","Dept. VLSI System Design, Ritsumeikan University Kusatsu, 525-8577 Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department VLSI System Design, Ritsumeikan University, Kusatsu, Japan","institution_ids":["https://openalex.org/I135768898"]},{"raw_affiliation_string":"Dept. VLSI System Design, Ritsumeikan University Kusatsu, 525-8577 Japan","institution_ids":["https://openalex.org/I135768898"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108511748","display_name":"Syuji Tsukiyama","orcid":null},"institutions":[{"id":"https://openalex.org/I96679780","display_name":"Chuo University","ror":"https://ror.org/03qvqb743","country_code":"JP","type":"education","lineage":["https://openalex.org/I96679780"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Syuji Tsukiyama","raw_affiliation_strings":["Department EECE, Chuo University, Tokyo, Japan","Dept. EECE, Chuo University Tokyo, 112-8551 Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department EECE, Chuo University, Tokyo, Japan","institution_ids":["https://openalex.org/I96679780"]},{"raw_affiliation_string":"Dept. EECE, Chuo University Tokyo, 112-8551 Japan","institution_ids":["https://openalex.org/I96679780"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.1801758,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"531","issue":null,"first_page":"703","last_page":"706"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6108683943748474},{"id":"https://openalex.org/keywords/decoupling","display_name":"Decoupling (probability)","score":0.5707533359527588},{"id":"https://openalex.org/keywords/grid","display_name":"Grid","score":0.5603499412536621},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.5148445963859558},{"id":"https://openalex.org/keywords/power-grid","display_name":"Power grid","score":0.4818909764289856},{"id":"https://openalex.org/keywords/manufacturing-cost","display_name":"Manufacturing cost","score":0.4816288352012634},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.44934403896331787},{"id":"https://openalex.org/keywords/power-network-design","display_name":"Power network design","score":0.4427235722541809},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.4374512732028961},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.4211944341659546},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.37753596901893616},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2493581473827362},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1478603482246399},{"id":"https://openalex.org/keywords/control-engineering","display_name":"Control engineering","score":0.13155320286750793},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1202014684677124},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11099007725715637}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6108683943748474},{"id":"https://openalex.org/C205606062","wikidata":"https://www.wikidata.org/wiki/Q5249645","display_name":"Decoupling (probability)","level":2,"score":0.5707533359527588},{"id":"https://openalex.org/C187691185","wikidata":"https://www.wikidata.org/wiki/Q2020720","display_name":"Grid","level":2,"score":0.5603499412536621},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.5148445963859558},{"id":"https://openalex.org/C2983254600","wikidata":"https://www.wikidata.org/wiki/Q1096907","display_name":"Power grid","level":3,"score":0.4818909764289856},{"id":"https://openalex.org/C2778337023","wikidata":"https://www.wikidata.org/wiki/Q6753108","display_name":"Manufacturing cost","level":2,"score":0.4816288352012634},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.44934403896331787},{"id":"https://openalex.org/C164565468","wikidata":"https://www.wikidata.org/wiki/Q7236535","display_name":"Power network design","level":3,"score":0.4427235722541809},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.4374512732028961},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.4211944341659546},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.37753596901893616},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2493581473827362},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1478603482246399},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.13155320286750793},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1202014684677124},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11099007725715637},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ecctd.2009.5275075","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2009.5275075","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 European Conference on Circuit Theory and Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W161930826","https://openalex.org/W1809870941","https://openalex.org/W1969705595","https://openalex.org/W2036759622","https://openalex.org/W2112148124","https://openalex.org/W2131531841","https://openalex.org/W2158728973","https://openalex.org/W2162135665","https://openalex.org/W4253058520","https://openalex.org/W6642744464"],"related_works":["https://openalex.org/W2152950565","https://openalex.org/W1617565119","https://openalex.org/W160381218","https://openalex.org/W2354365353","https://openalex.org/W2512958550","https://openalex.org/W2329266651","https://openalex.org/W3103825105","https://openalex.org/W2004102934","https://openalex.org/W4366455350","https://openalex.org/W2972236120"],"abstract_inverted_index":{"Power":[0],"grid":[1],"optimization":[2,45],"is":[3,46,58],"required":[4],"to":[5,59],"minimize":[6],"the":[7,24,34,52,56,61],"risks":[8],"of":[9,37,51,64,77],"timing":[10,41],"error":[11,42],"by":[12,16,23,32],"IR":[13],"drop,":[14],"defects":[15],"electro":[17],"migration":[18],"(EM),":[19],"and":[20,40,55],"manufacturing":[21,38],"cost":[22,79],"chip":[25],"size.":[26],"We":[27],"propose":[28],"a":[29,78,83],"new":[30],"approach":[31,74],"observing":[33],"direct":[35],"objectives":[36],"cost,":[39],"risk.":[43],"The":[44],"executed":[47],"in":[48],"early":[49],"phase":[50],"physical":[53],"design,":[54],"purpose":[57],"find":[60],"rough":[62],"budget":[63],"decoupling":[65],"capacitors":[66],"that":[67],"may":[68],"cause":[69],"block":[70],"size":[71],"increase.":[72],"This":[73],"enables":[75],"selection":[76],"sensitive":[80,85],"result":[81],"or":[82],"performance":[84],"result.":[86]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}