{"id":"https://openalex.org/W2162771183","doi":"https://doi.org/10.1109/ecctd.2009.5275071","title":"A generic reconfigurable array specification and programming environment (GRASPER)","display_name":"A generic reconfigurable array specification and programming environment (GRASPER)","publication_year":2009,"publication_date":"2009-08-01","ids":{"openalex":"https://openalex.org/W2162771183","doi":"https://doi.org/10.1109/ecctd.2009.5275071","mag":"2162771183"},"language":"en","primary_location":{"id":"doi:10.1109/ecctd.2009.5275071","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2009.5275071","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 European Conference on Circuit Theory and Design","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041703213","display_name":"Fa\u00edk Ba\u015fkaya","orcid":"https://orcid.org/0000-0001-6743-3992"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Faik Baskaya","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033437141","display_name":"David V. Anderson","orcid":"https://orcid.org/0000-0002-8571-4613"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David V. Anderson","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5105781337","display_name":"P. Hasler","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Paul Hasler","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052950521","display_name":"Sung Kyu Lim","orcid":"https://orcid.org/0000-0002-2267-5282"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sung Kyu Lim","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"17","issue":null,"first_page":"619","last_page":"622"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-analog-array","display_name":"Field-programmable analog array","score":0.7649840712547302},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7106167078018188},{"id":"https://openalex.org/keywords/parasitic-extraction","display_name":"Parasitic extraction","score":0.6267276406288147},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.6242244243621826},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5666855573654175},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.5108420252799988},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4850722849369049},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4580170214176178},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.430990993976593},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3593042194843292},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3578280508518219},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.28399527072906494},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18875133991241455},{"id":"https://openalex.org/keywords/analog-signal","display_name":"Analog signal","score":0.168519526720047},{"id":"https://openalex.org/keywords/analog-multiplier","display_name":"Analog multiplier","score":0.14746633172035217},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11350062489509583},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.11005103588104248}],"concepts":[{"id":"https://openalex.org/C149128552","wikidata":"https://www.wikidata.org/wiki/Q380201","display_name":"Field-programmable analog array","level":5,"score":0.7649840712547302},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7106167078018188},{"id":"https://openalex.org/C159818811","wikidata":"https://www.wikidata.org/wiki/Q7135947","display_name":"Parasitic extraction","level":2,"score":0.6267276406288147},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.6242244243621826},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5666855573654175},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.5108420252799988},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4850722849369049},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4580170214176178},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.430990993976593},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3593042194843292},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3578280508518219},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.28399527072906494},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18875133991241455},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.168519526720047},{"id":"https://openalex.org/C98142538","wikidata":"https://www.wikidata.org/wiki/Q485005","display_name":"Analog multiplier","level":4,"score":0.14746633172035217},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11350062489509583},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.11005103588104248},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ecctd.2009.5275071","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2009.5275071","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 European Conference on Circuit Theory and Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5600000023841858}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1794590847","https://openalex.org/W1859405014","https://openalex.org/W2106267865","https://openalex.org/W2123962621","https://openalex.org/W2124419647","https://openalex.org/W2128890914","https://openalex.org/W2136358791","https://openalex.org/W2139637699","https://openalex.org/W2148271369","https://openalex.org/W2153580689","https://openalex.org/W2153960176","https://openalex.org/W2160184383","https://openalex.org/W2160474882","https://openalex.org/W2168153801","https://openalex.org/W4232853208"],"related_works":["https://openalex.org/W2028682231","https://openalex.org/W1536393281","https://openalex.org/W2184193821","https://openalex.org/W2101485986","https://openalex.org/W2254292019","https://openalex.org/W1975676954","https://openalex.org/W2547030302","https://openalex.org/W1576659905","https://openalex.org/W1471373344","https://openalex.org/W2363194225"],"abstract_inverted_index":{"Modern":[0],"advances":[1],"in":[2,44,99,112],"reconfigurable":[3],"technologies":[4],"are":[5,69],"allowing":[6],"analog":[7,20,31,37,101],"circuit":[8,97],"designers":[9],"to":[10,54,116],"benefit":[11],"from":[12],"the":[13,24,55,73,83,89,100,135,155],"computational":[14],"flexibility":[15],"provided":[16],"by":[17],"large-scale":[18],"field-programmable":[19],"arrays":[21],"(FPAAs).":[22],"With":[23],"component":[25],"density":[26],"of":[27,82,93,134,146],"these":[28,67],"devices,":[29],"small":[30],"circuits":[32],"as":[33,35],"well":[34],"larger":[36],"systems":[38],"can":[39,141,152],"be":[40,107],"synthesized":[41],"and":[42,48,63,128,149],"tested":[43],"a":[45,50,118,123,129,143],"shorter":[46],"time":[47],"at":[49],"lower":[51],"cost":[52],"compared":[53],"full":[56],"design":[57],"cycle.":[58],"However,":[59],"automated":[60],"development":[61],"platforms":[62],"CAD":[64],"tools":[65,76],"for":[66,77,86,132],"devices":[68],"far":[70],"fewer":[71],"than":[72],"physical":[74,119],"synthesis":[75,120,136,139],"their":[78],"digital":[79],"counterparts.":[80],"One":[81],"major":[84],"reasons":[85],"this":[87,113],"is":[88,115],"considerably":[90],"higher":[91],"impact":[92],"interconnect":[94],"parasitics":[95],"on":[96],"functionality":[98],"domain;":[102],"therefore,":[103],"performance":[104,156],"metrics":[105],"must":[106],"monitored":[108],"closely.":[109],"Our":[110,138],"goal":[111],"paper":[114],"present":[117],"framework":[121],"with":[122],"generic":[124],"architecture":[125],"specification":[126],"interface":[127],"parasitic":[130],"extractor":[131],"verification":[133],"results.":[137],"tool":[140],"support":[142],"wide":[144],"range":[145],"FPAA":[147],"architectures":[148],"our":[150],"simulations":[151],"successfully":[153],"predict":[154],"metrics.":[157]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
