{"id":"https://openalex.org/W2150446686","doi":"https://doi.org/10.1109/ecctd.2009.5275065","title":"SAT-based ATPG testing of inter- and intra-gate bridging faults","display_name":"SAT-based ATPG testing of inter- and intra-gate bridging faults","publication_year":2009,"publication_date":"2009-08-01","ids":{"openalex":"https://openalex.org/W2150446686","doi":"https://doi.org/10.1109/ecctd.2009.5275065","mag":"2150446686"},"language":"en","primary_location":{"id":"doi:10.1109/ecctd.2009.5275065","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2009.5275065","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 European Conference on Circuit Theory and Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111964542","display_name":"Tom Nakura","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Tom Nakura","raw_affiliation_strings":["VDEC, University of Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"VDEC, University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080594146","display_name":"Yutaro Tatemura","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yutaro Tatemura","raw_affiliation_strings":["Department of Electronic Engineering, University of Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008766097","display_name":"G\u00f6rschwin Fey","orcid":"https://orcid.org/0000-0001-6433-6265"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Gorschwin Fey","raw_affiliation_strings":["D2T VDEC, University of Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"D2T VDEC, University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102900006","display_name":"Makoto Ikeda","orcid":"https://orcid.org/0000-0002-6644-4224"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Makoto Ikeda","raw_affiliation_strings":["VDEC, University of Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"VDEC, University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103025045","display_name":"Satoshi Komatsu","orcid":"https://orcid.org/0000-0002-9180-9053"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Satoshi Komatsu","raw_affiliation_strings":["D2T VDEC, University of Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"D2T VDEC, University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028680447","display_name":"Kunihiro Asada","orcid":"https://orcid.org/0000-0002-1150-0241"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kunihiro Asada","raw_affiliation_strings":["VDEC, University of Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"VDEC, University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5111964542"],"corresponding_institution_ids":["https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.16655155,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"643","last_page":"646"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/iddq-testing","display_name":"Iddq testing","score":0.9548602104187012},{"id":"https://openalex.org/keywords/bridging","display_name":"Bridging (networking)","score":0.9006651639938354},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.7588186264038086},{"id":"https://openalex.org/keywords/boolean-satisfiability-problem","display_name":"Boolean satisfiability problem","score":0.6999046206474304},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.577146053314209},{"id":"https://openalex.org/keywords/satisfiability","display_name":"Satisfiability","score":0.4702775776386261},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.44945114850997925},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.4395025372505188},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4380049705505371},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.42696523666381836},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.360567569732666},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23198512196540833},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.1022273600101471},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.09516152739524841},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.06932127475738525}],"concepts":[{"id":"https://openalex.org/C206678392","wikidata":"https://www.wikidata.org/wiki/Q5987815","display_name":"Iddq testing","level":3,"score":0.9548602104187012},{"id":"https://openalex.org/C174348530","wikidata":"https://www.wikidata.org/wiki/Q188635","display_name":"Bridging (networking)","level":2,"score":0.9006651639938354},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.7588186264038086},{"id":"https://openalex.org/C6943359","wikidata":"https://www.wikidata.org/wiki/Q875276","display_name":"Boolean satisfiability problem","level":2,"score":0.6999046206474304},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.577146053314209},{"id":"https://openalex.org/C168773769","wikidata":"https://www.wikidata.org/wiki/Q1350299","display_name":"Satisfiability","level":2,"score":0.4702775776386261},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.44945114850997925},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.4395025372505188},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4380049705505371},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.42696523666381836},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.360567569732666},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23198512196540833},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.1022273600101471},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.09516152739524841},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.06932127475738525},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ecctd.2009.5275065","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2009.5275065","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 European Conference on Circuit Theory and Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1518705996","https://openalex.org/W1767671217","https://openalex.org/W2062897452","https://openalex.org/W2069520100","https://openalex.org/W2099807755","https://openalex.org/W2124130611","https://openalex.org/W2127145135","https://openalex.org/W2134925363","https://openalex.org/W2135613306","https://openalex.org/W2140365332","https://openalex.org/W2157748808","https://openalex.org/W2160444875","https://openalex.org/W2169468177","https://openalex.org/W2174547182"],"related_works":["https://openalex.org/W2082374775","https://openalex.org/W2538904067","https://openalex.org/W2117563988","https://openalex.org/W1549680942","https://openalex.org/W2181952921","https://openalex.org/W1933196597","https://openalex.org/W2120257283","https://openalex.org/W2132684947","https://openalex.org/W1412895167","https://openalex.org/W2165817266"],"abstract_inverted_index":{"This":[0,33],"paper":[1],"presents":[2],"an":[3,47],"ATPG":[4],"framework":[5,17],"for":[6,50,53],"IDDQ":[7,54],"testing":[8,55],"of":[9,56],"both":[10,57],"intra-":[11,58],"and":[12,21,59],"inter-gate":[13,60],"bridging":[14,61],"faults.":[15],"The":[16],"integrates":[18],"random":[19],"simulation":[20],"a":[22,36],"deterministic":[23],"stage":[24],"using":[25],"Boolean":[26],"SATisfiability":[27],"(SAT)":[28],"as":[29],"the":[30],"underlying":[31],"engine.":[32],"decides":[34],"whether":[35],"fault":[37,62],"is":[38],"testable":[39],"or":[40],"untestable.":[41],"In":[42],"this":[43],"way,":[44],"we":[45],"conduct":[46],"exact":[48],"search":[49],"test":[51],"patterns":[52],"detection.":[63]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}