{"id":"https://openalex.org/W2137349086","doi":"https://doi.org/10.1109/ecctd.2009.5274987","title":"Topology selection of FPGA look-up tables for low-leakage operation","display_name":"Topology selection of FPGA look-up tables for low-leakage operation","publication_year":2009,"publication_date":"2009-08-01","ids":{"openalex":"https://openalex.org/W2137349086","doi":"https://doi.org/10.1109/ecctd.2009.5274987","mag":"2137349086"},"language":"en","primary_location":{"id":"doi:10.1109/ecctd.2009.5274987","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2009.5274987","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 European Conference on Circuit Theory and Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109679886","display_name":"Pradeep S. Nair","orcid":null},"institutions":[{"id":"https://openalex.org/I45438204","display_name":"The University of Texas at San Antonio","ror":"https://ror.org/01kd65564","country_code":"US","type":"education","lineage":["https://openalex.org/I45438204"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Pradeep S. Nair","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas, San Antonio, San Antonio, TX, USA","Department of Electrical and Computer Engineering, University of Texas at San Antonio, San Antonio, TX \u2013 78249, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas, San Antonio, San Antonio, TX, USA","institution_ids":["https://openalex.org/I45438204"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at San Antonio, San Antonio, TX \u2013 78249, USA","institution_ids":["https://openalex.org/I45438204"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053166452","display_name":"Santosh Koppa","orcid":null},"institutions":[{"id":"https://openalex.org/I45438204","display_name":"The University of Texas at San Antonio","ror":"https://ror.org/01kd65564","country_code":"US","type":"education","lineage":["https://openalex.org/I45438204"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Santosh Koppa","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas, San Antonio, San Antonio, TX, USA","Department of Electrical and Computer Engineering, University of Texas at San Antonio, San Antonio, TX \u2013 78249, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas, San Antonio, San Antonio, TX, USA","institution_ids":["https://openalex.org/I45438204"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at San Antonio, San Antonio, TX \u2013 78249, USA","institution_ids":["https://openalex.org/I45438204"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010151984","display_name":"Eugene John","orcid":"https://orcid.org/0000-0001-9494-4894"},"institutions":[{"id":"https://openalex.org/I45438204","display_name":"The University of Texas at San Antonio","ror":"https://ror.org/01kd65564","country_code":"US","type":"education","lineage":["https://openalex.org/I45438204"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Eugene B. John","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas, San Antonio, San Antonio, TX, USA","Department of Electrical and Computer Engineering, University of Texas at San Antonio, San Antonio, TX \u2013 78249, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas, San Antonio, San Antonio, TX, USA","institution_ids":["https://openalex.org/I45438204"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at San Antonio, San Antonio, TX \u2013 78249, USA","institution_ids":["https://openalex.org/I45438204"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5067236813","display_name":"Dhireesha Kudithipudi","orcid":"https://orcid.org/0000-0003-4462-5224"},"institutions":[{"id":"https://openalex.org/I155173764","display_name":"Rochester Institute of Technology","ror":"https://ror.org/00v4yb702","country_code":"US","type":"education","lineage":["https://openalex.org/I155173764"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dhireesha Kudithipudi","raw_affiliation_strings":["Department of Computer Engineering, Rochester Institute of Technology, Rochester, NY, USA","Department of Computer Engineering, Rochester Institute of Technology, Rochester, NY, 14623, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Rochester Institute of Technology, Rochester, NY, USA","institution_ids":["https://openalex.org/I155173764"]},{"raw_affiliation_string":"Department of Computer Engineering, Rochester Institute of Technology, Rochester, NY, 14623, USA","institution_ids":["https://openalex.org/I155173764"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5109679886"],"corresponding_institution_ids":["https://openalex.org/I45438204"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.15321183,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"73","last_page":"76"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.889067530632019},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.716338574886322},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.6815475225448608},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.6735992431640625},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.5943238735198975},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5537590980529785},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.5412914156913757},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.535365104675293},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.490878164768219},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.47850409150123596},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.4686533808708191},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.42503881454467773},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.4113166332244873},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4067627787590027},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3953265845775604},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.38916900753974915},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.33034566044807434},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3100464940071106},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.15673458576202393},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.14346718788146973},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.13770607113838196},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.13452431559562683}],"concepts":[{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.889067530632019},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.716338574886322},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.6815475225448608},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.6735992431640625},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.5943238735198975},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5537590980529785},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.5412914156913757},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.535365104675293},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.490878164768219},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.47850409150123596},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.4686533808708191},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.42503881454467773},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.4113166332244873},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4067627787590027},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3953265845775604},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.38916900753974915},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.33034566044807434},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3100464940071106},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.15673458576202393},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.14346718788146973},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.13770607113838196},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.13452431559562683},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ecctd.2009.5274987","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2009.5274987","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 European Conference on Circuit Theory and Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.6000000238418579}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1497276254","https://openalex.org/W1761143336","https://openalex.org/W1970278706","https://openalex.org/W2108880814","https://openalex.org/W2122035961","https://openalex.org/W2135987877","https://openalex.org/W2150098004","https://openalex.org/W6676056936"],"related_works":["https://openalex.org/W1993197222","https://openalex.org/W1972355764","https://openalex.org/W3006681749","https://openalex.org/W2809889545","https://openalex.org/W1948588291","https://openalex.org/W3129152221","https://openalex.org/W2058461810","https://openalex.org/W2891188466","https://openalex.org/W2135286216","https://openalex.org/W1997318576"],"abstract_inverted_index":{"Modern":[0],"field-programmable":[1],"gate":[2],"arrays":[3],"(FPGAs)":[4],"are":[5,32,38,69],"increasingly":[6],"becoming":[7],"prone":[8],"to":[9,17,110],"leakage":[10,77,107],"power":[11,78],"dissipation,":[12],"which":[13,44],"can":[14],"be":[15],"attributed":[16],"their":[18],"flexibility":[19],"and":[20,53],"increasing":[21],"densities.":[22],"One":[23],"of":[24,29,64,106],"the":[25,35,39,51],"most":[26],"important":[27],"types":[28],"elements":[30],"that":[31,68,89],"used":[33],"throughout":[34],"FPGA":[36],"fabric":[37],"NMOS":[40],"pass-transistor":[41],"based":[42,70],"multiplexers,":[43],"play":[45],"a":[46,61,76,82,90],"prominent":[47],"role":[48],"in":[49],"both":[50],"logic":[52],"routing":[54],"blocks.":[55],"In":[56],"this":[57],"paper,":[58],"we":[59],"undertake":[60],"comparative":[62],"study":[63],"various":[65],"FPGA-LUT":[66],"topologies":[67],"on":[71],"different":[72],"constituent":[73],"multiplexers":[74,97,102],"from":[75],"dissipation":[79],"perspective,":[80],"for":[81],"45":[83],"nm":[84],"CMOS":[85],"process.":[86],"We":[87],"found":[88],"LUT":[91],"constructed":[92],"with":[93,99],"two":[94],"8:1":[95],"decoded":[96],"or":[98],"three":[100],"4:1":[101],"has":[103],"lesser":[104],"amount":[105],"when":[108],"compared":[109],"other":[111],"topologies.":[112]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}