{"id":"https://openalex.org/W2162009704","doi":"https://doi.org/10.1109/ecctd.2007.4529656","title":"Designing VFs by applying genetic algorithms from nullator-based descriptions","display_name":"Designing VFs by applying genetic algorithms from nullator-based descriptions","publication_year":2007,"publication_date":"2007-08-01","ids":{"openalex":"https://openalex.org/W2162009704","doi":"https://doi.org/10.1109/ecctd.2007.4529656","mag":"2162009704"},"language":"en","primary_location":{"id":"doi:10.1109/ecctd.2007.4529656","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2007.4529656","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 18th European Conference on Circuit Theory and Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063933849","display_name":"Esteban Tlelo\u2010Cuautle","orcid":"https://orcid.org/0000-0001-7187-4686"},"institutions":[{"id":"https://openalex.org/I39824353","display_name":"National Institute of Astrophysics, Optics and Electronics","ror":"https://ror.org/00bpmmc63","country_code":"MX","type":"facility","lineage":["https://openalex.org/I39824353"]}],"countries":["MX"],"is_corresponding":true,"raw_author_name":"E. Tlelo-Cuautle","raw_affiliation_strings":["INAOE, Tonantzintla, Puebla, MEXICO"],"affiliations":[{"raw_affiliation_string":"INAOE, Tonantzintla, Puebla, MEXICO","institution_ids":["https://openalex.org/I39824353"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019017222","display_name":"Miguel Aurelio Duarte Villase\u00f1or","orcid":"https://orcid.org/0000-0002-8858-8595"},"institutions":[{"id":"https://openalex.org/I39824353","display_name":"National Institute of Astrophysics, Optics and Electronics","ror":"https://ror.org/00bpmmc63","country_code":"MX","type":"facility","lineage":["https://openalex.org/I39824353"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"M.A. Duarte-Villasenor","raw_affiliation_strings":["INAOE, Puebla, MEXICO"],"affiliations":[{"raw_affiliation_string":"INAOE, Puebla, MEXICO","institution_ids":["https://openalex.org/I39824353"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045421340","display_name":"Carlos A. Reyes-Garc\u00eda","orcid":"https://orcid.org/0000-0003-4773-9585"},"institutions":[{"id":"https://openalex.org/I39824353","display_name":"National Institute of Astrophysics, Optics and Electronics","ror":"https://ror.org/00bpmmc63","country_code":"MX","type":"facility","lineage":["https://openalex.org/I39824353"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"C.A. Reyes-Garcia","raw_affiliation_strings":["INAOE, Tonantzintla, Puebla, MEXICO"],"affiliations":[{"raw_affiliation_string":"INAOE, Tonantzintla, Puebla, MEXICO","institution_ids":["https://openalex.org/I39824353"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085623061","display_name":"Mourad Fakhfakh","orcid":"https://orcid.org/0000-0003-2460-9462"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"M. Fakhfakh","raw_affiliation_strings":["ENIS. Laboratoire d'\u00e9lectronique et des technologies de l'information, Sfax, TUNISIA"],"affiliations":[{"raw_affiliation_string":"ENIS. Laboratoire d'\u00e9lectronique et des technologies de l'information, Sfax, TUNISIA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111432820","display_name":"M. Loulou","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"M. Loulou","raw_affiliation_strings":["ENIS. Laboratoire d'\u00e9lectronique et des technologies de l'information, Sfax, TUNISIA"],"affiliations":[{"raw_affiliation_string":"ENIS. Laboratoire d'\u00e9lectronique et des technologies de l'information, Sfax, TUNISIA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032954605","display_name":"C. S\u00e1nchez\u2010L\u00f3pez","orcid":"https://orcid.org/0000-0002-3214-5832"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"C. Sanchez-Lopez","raw_affiliation_strings":["UAT. Department of Electronics, Mexico"],"affiliations":[{"raw_affiliation_string":"UAT. Department of Electronics, Mexico","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5042679498","display_name":"Gerardo Reyes-Salgado","orcid":null},"institutions":[{"id":"https://openalex.org/I4210138655","display_name":"Centro Nacional de Investigaci\u00f3n y Desarrollo Tecnol\u00f3gico","ror":"https://ror.org/0314ecq26","country_code":"MX","type":"facility","lineage":["https://openalex.org/I4210138655"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"G. Reyes-Salgado","raw_affiliation_strings":["CENIDET. Department of Computer Sciences","Department of Computer Sciences, CENIDET, Mexico"],"affiliations":[{"raw_affiliation_string":"CENIDET. Department of Computer Sciences","institution_ids":["https://openalex.org/I4210138655"]},{"raw_affiliation_string":"Department of Computer Sciences, CENIDET, Mexico","institution_ids":["https://openalex.org/I4210138655"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5063933849"],"corresponding_institution_ids":["https://openalex.org/I39824353"],"apc_list":null,"apc_paid":null,"fwci":1.5667,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.83649424,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"555","last_page":"558"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7114248275756836},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6792495250701904},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.5875895619392395},{"id":"https://openalex.org/keywords/genetic-algorithm","display_name":"Genetic algorithm","score":0.5465031862258911},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.5127878785133362},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.4412871301174164},{"id":"https://openalex.org/keywords/encoding","display_name":"Encoding (memory)","score":0.4169155955314636},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.40338853001594543},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.39868783950805664},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3942410349845886},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3905789256095886},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.1974666714668274},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18241983652114868},{"id":"https://openalex.org/keywords/machine-learning","display_name":"Machine learning","score":0.14427655935287476},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.10247448086738586}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7114248275756836},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6792495250701904},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.5875895619392395},{"id":"https://openalex.org/C8880873","wikidata":"https://www.wikidata.org/wiki/Q187787","display_name":"Genetic algorithm","level":2,"score":0.5465031862258911},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.5127878785133362},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.4412871301174164},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.4169155955314636},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.40338853001594543},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.39868783950805664},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3942410349845886},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3905789256095886},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.1974666714668274},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18241983652114868},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.14427655935287476},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.10247448086738586},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ecctd.2007.4529656","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2007.4529656","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 18th European Conference on Circuit Theory and Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W563978581","https://openalex.org/W566385658","https://openalex.org/W1524759419","https://openalex.org/W1549744172","https://openalex.org/W1594120130","https://openalex.org/W1884783164","https://openalex.org/W1964816141","https://openalex.org/W1998021591","https://openalex.org/W2002347827","https://openalex.org/W2002679534","https://openalex.org/W2013286089","https://openalex.org/W2016576374","https://openalex.org/W2063978318","https://openalex.org/W2096255496","https://openalex.org/W2162119956","https://openalex.org/W2501261048","https://openalex.org/W6639217578"],"related_works":["https://openalex.org/W2375311683","https://openalex.org/W2366062860","https://openalex.org/W2373777250","https://openalex.org/W2353956655","https://openalex.org/W2020653254","https://openalex.org/W2010454064","https://openalex.org/W2352072014","https://openalex.org/W217279133","https://openalex.org/W2393487946","https://openalex.org/W2895079552"],"abstract_inverted_index":{"An":[0],"automatic":[1,21],"method":[2,42],"is":[3,17,68],"proposed":[4,41],"to":[5,29,71,87,94,109],"design":[6,30,110],"CMOS":[7,61],"compatible":[8],"voltage":[9],"followers":[10],"(VFs)":[11],"by":[12,33,58,74],"applying":[13],"genetic":[14],"algorithms.":[15],"It":[16],"described":[18,69],"how":[19,70,86],"an":[20],"system":[22],"can":[23],"deals":[24],"with":[25,104],"huge":[26],"search":[27],"spaces":[28],"practical":[31],"VFs":[32,73,108],"performing":[34],"evolutionary":[35],"operations":[36],"from":[37],"nullator-based":[38],"descriptions.":[39],"The":[40],"consists":[43],"of":[44,49,54,63,83,107],"three":[45,77,81],"main":[46,78],"steps:":[47],"generation":[48],"the":[50,76,105],"small-signal":[51],"circuitry,":[52],"addition":[53],"biases,":[55],"and":[56,85,91],"sizing":[57],"using":[59],"standard":[60],"technology":[62],"0.35":[64],"mum.":[65],"Furthermore,":[66],"it":[67],"synthesize":[72],"codifying":[75],"steps":[79],"into":[80],"kinds":[82],"genes,":[84],"select":[88],"small-signal,":[89],"biased,":[90],"sized":[92],"topologies":[93],"generate":[95],"potential":[96],"solutions.":[97],"Finally,":[98],"several":[99],"applications":[100],"are":[101],"discussed":[102],"along":[103],"evolution":[106],"current":[111],"conveyors.":[112]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}