{"id":"https://openalex.org/W2113696963","doi":"https://doi.org/10.1109/ecctd.2007.4529652","title":"CMOS Miller OTA with Body-Biased Output Stage","display_name":"CMOS Miller OTA with Body-Biased Output Stage","publication_year":2007,"publication_date":"2007-08-01","ids":{"openalex":"https://openalex.org/W2113696963","doi":"https://doi.org/10.1109/ecctd.2007.4529652","mag":"2113696963"},"language":"en","primary_location":{"id":"doi:10.1109/ecctd.2007.4529652","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2007.4529652","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 18th European Conference on Circuit Theory and Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078615947","display_name":"Alfio Dario Grasso","orcid":"https://orcid.org/0000-0002-5707-9683"},"institutions":[{"id":"https://openalex.org/I39063666","display_name":"University of Catania","ror":"https://ror.org/03a64bh57","country_code":"IT","type":"education","lineage":["https://openalex.org/I39063666"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"A. D. Grasso","raw_affiliation_strings":["Dipartimento di Ingegneria Elettrica, Elettronica e dei Sistemi (DIEES), Universit\u00e0 di Catania, Catania, Italy","Dip. di Ing. Elettr., Univ. di Catania, Catania"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Elettrica, Elettronica e dei Sistemi (DIEES), Universit\u00e0 di Catania, Catania, Italy","institution_ids":["https://openalex.org/I39063666"]},{"raw_affiliation_string":"Dip. di Ing. Elettr., Univ. di Catania, Catania","institution_ids":["https://openalex.org/I39063666"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004729135","display_name":"Salvatore Pennisi","orcid":"https://orcid.org/0000-0002-5803-484X"},"institutions":[{"id":"https://openalex.org/I39063666","display_name":"University of Catania","ror":"https://ror.org/03a64bh57","country_code":"IT","type":"education","lineage":["https://openalex.org/I39063666"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"S. Pennisi","raw_affiliation_strings":["Dipartimento di Ingegneria Elettrica, Elettronica e dei Sistemi (DIEES), Universit\u00e0 di Catania, Catania, Italy","Dip. di Ing. Elettr., Univ. di Catania, Catania"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Elettrica, Elettronica e dei Sistemi (DIEES), Universit\u00e0 di Catania, Catania, Italy","institution_ids":["https://openalex.org/I39063666"]},{"raw_affiliation_string":"Dip. di Ing. Elettr., Univ. di Catania, Catania","institution_ids":["https://openalex.org/I39063666"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030782483","display_name":"Francesco Centurelli","orcid":"https://orcid.org/0000-0003-3880-2546"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"F. Centurelli","raw_affiliation_strings":["Dipartimento di Ingegneria Elettronica (DIE), Universit\u00e0 di Roma La Sapienza, Rome, Italy","Dip. di Ingegneria Elettronica (DIE), Universit\u00e0 di Roma \u00bfLa Sapienza\u00bf, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Elettronica (DIE), Universit\u00e0 di Roma La Sapienza, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"Dip. di Ingegneria Elettronica (DIE), Universit\u00e0 di Roma \u00bfLa Sapienza\u00bf, Italy","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010336494","display_name":"Giuseppe Scotti","orcid":"https://orcid.org/0000-0002-5650-8212"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G. Scotti","raw_affiliation_strings":["Dipartimento di Ingegneria Elettronica (DIE), Universit\u00e0 di Roma La Sapienza, Rome, Italy","Dip. di Ingegneria Elettronica (DIE), Universit\u00e0 di Roma \u00bfLa Sapienza\u00bf, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Elettronica (DIE), Universit\u00e0 di Roma La Sapienza, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"Dip. di Ingegneria Elettronica (DIE), Universit\u00e0 di Roma \u00bfLa Sapienza\u00bf, Italy","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068452963","display_name":"Alessandro Trifiletti","orcid":"https://orcid.org/0000-0001-6231-4273"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"A. Trifiletti","raw_affiliation_strings":["Dipartimento di Ingegneria Elettronica (DIE), Universit\u00e0 di Roma La Sapienza, Rome, Italy","Dip. di Ingegneria Elettronica (DIE), Universit\u00e0 di Roma \u00bfLa Sapienza\u00bf, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Elettronica (DIE), Universit\u00e0 di Roma La Sapienza, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"Dip. di Ingegneria Elettronica (DIE), Universit\u00e0 di Roma \u00bfLa Sapienza\u00bf, Italy","institution_ids":["https://openalex.org/I861853513"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5078615947"],"corresponding_institution_ids":["https://openalex.org/I39063666"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.16491096,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"539","last_page":"542"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.8532412052154541},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.537672758102417},{"id":"https://openalex.org/keywords/swing","display_name":"Swing","score":0.5231764912605286},{"id":"https://openalex.org/keywords/current-sense-amplifier","display_name":"Current sense amplifier","score":0.5080187320709229},{"id":"https://openalex.org/keywords/biasing","display_name":"Biasing","score":0.503476083278656},{"id":"https://openalex.org/keywords/stage","display_name":"Stage (stratigraphy)","score":0.4916744828224182},{"id":"https://openalex.org/keywords/operational-amplifier","display_name":"Operational amplifier","score":0.4872983694076538},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.47766217589378357},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44823169708251953},{"id":"https://openalex.org/keywords/single-stage","display_name":"Single stage","score":0.4120589792728424},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.40753233432769775},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3989759683609009},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2952331304550171}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.8532412052154541},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.537672758102417},{"id":"https://openalex.org/C65655974","wikidata":"https://www.wikidata.org/wiki/Q14867674","display_name":"Swing","level":2,"score":0.5231764912605286},{"id":"https://openalex.org/C182442803","wikidata":"https://www.wikidata.org/wiki/Q5195113","display_name":"Current sense amplifier","level":5,"score":0.5080187320709229},{"id":"https://openalex.org/C20254490","wikidata":"https://www.wikidata.org/wiki/Q719550","display_name":"Biasing","level":3,"score":0.503476083278656},{"id":"https://openalex.org/C146357865","wikidata":"https://www.wikidata.org/wiki/Q1123245","display_name":"Stage (stratigraphy)","level":2,"score":0.4916744828224182},{"id":"https://openalex.org/C145366948","wikidata":"https://www.wikidata.org/wiki/Q178947","display_name":"Operational amplifier","level":4,"score":0.4872983694076538},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.47766217589378357},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44823169708251953},{"id":"https://openalex.org/C3020376581","wikidata":"https://www.wikidata.org/wiki/Q16866784","display_name":"Single stage","level":2,"score":0.4120589792728424},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.40753233432769775},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3989759683609009},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2952331304550171},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C146978453","wikidata":"https://www.wikidata.org/wiki/Q3798668","display_name":"Aerospace engineering","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/ecctd.2007.4529652","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2007.4529652","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 18th European Conference on Circuit Theory and Design","raw_type":"proceedings-article"},{"id":"pmh:oai:iris.uniroma1.it:11573/234505","is_oa":false,"landing_page_url":"http://www.scopus.com/inward/record.url?eid=2-s2.0-49749145590&partnerID=65&md5=f3f8ebe0032f708fbc243fca99273a54","pdf_url":null,"source":{"id":"https://openalex.org/S4377196107","display_name":"IRIS Research product catalog (Sapienza University of Rome)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8399999737739563,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1536945048","https://openalex.org/W1541751756","https://openalex.org/W1576972161","https://openalex.org/W1594863824","https://openalex.org/W1964034808","https://openalex.org/W2125337150","https://openalex.org/W2142641748"],"related_works":["https://openalex.org/W4240158017","https://openalex.org/W2134309623","https://openalex.org/W2348781660","https://openalex.org/W4234592241","https://openalex.org/W2042716270","https://openalex.org/W4238493253","https://openalex.org/W1481948391","https://openalex.org/W2094356678","https://openalex.org/W2165132866","https://openalex.org/W2369276692"],"abstract_inverted_index":{"A":[0],"bias":[1],"technique":[2],"for":[3],"low-voltage":[4],"class":[5],"AB":[6],"amplifiers":[7],"is":[8],"presented.":[9],"The":[10],"approach":[11],"exploits":[12],"the":[13,18,35,50,53],"bulk":[14],"terminal":[15],"to":[16],"set":[17],"output":[19],"quiescent":[20],"current":[21],"of":[22,52],"a":[23,29,41,45],"two-stage":[24],"class-AB":[25],"CMOS":[26,47],"OTA":[27],"in":[28],"reliable":[30],"manner":[31],"and":[32],"without":[33],"reducing":[34],"maximum":[36],"swing":[37],"capability.":[38],"Simulations":[39],"on":[40],"designed":[42],"example":[43],"using":[44],"0.25-mum":[46],"process":[48],"show":[49],"viability":[51],"approach.":[54]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}