{"id":"https://openalex.org/W2100341489","doi":"https://doi.org/10.1109/ecctd.2007.4529558","title":"Reduction of simultaneous switching noise in analog signal band","display_name":"Reduction of simultaneous switching noise in analog signal band","publication_year":2007,"publication_date":"2007-08-01","ids":{"openalex":"https://openalex.org/W2100341489","doi":"https://doi.org/10.1109/ecctd.2007.4529558","mag":"2100341489"},"language":"en","primary_location":{"id":"doi:10.1109/ecctd.2007.4529558","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2007.4529558","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 18th European Conference on Circuit Theory and Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080288401","display_name":"Erik Backenius","orcid":null},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":true,"raw_author_name":"E. Backenius","raw_affiliation_strings":["Department of Electrical Engineering, Linkoping University, Sweden","[Dept. of Electr. Eng., Linkoping Univ., Linkoping]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Linkoping University, Sweden","institution_ids":["https://openalex.org/I102134673"]},{"raw_affiliation_string":"[Dept. of Electr. Eng., Linkoping Univ., Linkoping]","institution_ids":["https://openalex.org/I102134673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047505166","display_name":"Mark Vesterbacka","orcid":null},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"M. Vesterbacka","raw_affiliation_strings":["Department of Electrical Engineering, Linkoping University, Sweden","[Dept. of Electr. Eng., Linkoping Univ., Linkoping]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Linkoping University, Sweden","institution_ids":["https://openalex.org/I102134673"]},{"raw_affiliation_string":"[Dept. of Electr. Eng., Linkoping Univ., Linkoping]","institution_ids":["https://openalex.org/I102134673"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5027798138","display_name":"V. B. Settu","orcid":null},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"V. B. Settu","raw_affiliation_strings":["Department of Electrical Engineering, Linkoping University, Sweden","[Dept. of Electr. Eng., Linkoping Univ., Linkoping]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Linkoping University, Sweden","institution_ids":["https://openalex.org/I102134673"]},{"raw_affiliation_string":"[Dept. of Electr. Eng., Linkoping Univ., Linkoping]","institution_ids":["https://openalex.org/I102134673"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5080288401"],"corresponding_institution_ids":["https://openalex.org/I102134673"],"apc_list":null,"apc_paid":null,"fwci":0.2611,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.62707764,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"148","last_page":"151"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6199369430541992},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5681067109107971},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5027966499328613},{"id":"https://openalex.org/keywords/cascode","display_name":"Cascode","score":0.4782599210739136},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.46344685554504395},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.45104125142097473},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.45093947649002075},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.43697136640548706},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.42823922634124756},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.41682910919189453},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4122281074523926},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.3778834044933319},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23654913902282715},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.18788382411003113},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.12685495615005493}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6199369430541992},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5681067109107971},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5027966499328613},{"id":"https://openalex.org/C2775946640","wikidata":"https://www.wikidata.org/wiki/Q1735017","display_name":"Cascode","level":4,"score":0.4782599210739136},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.46344685554504395},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.45104125142097473},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.45093947649002075},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.43697136640548706},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.42823922634124756},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.41682910919189453},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4122281074523926},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.3778834044933319},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23654913902282715},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.18788382411003113},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.12685495615005493},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ecctd.2007.4529558","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2007.4529558","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 18th European Conference on Circuit Theory and Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8899999856948853,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W562583503","https://openalex.org/W1638329847","https://openalex.org/W1966430082","https://openalex.org/W2000260960","https://openalex.org/W2138134203","https://openalex.org/W2144874706","https://openalex.org/W2169071786"],"related_works":["https://openalex.org/W2290310756","https://openalex.org/W2063994266","https://openalex.org/W1980349267","https://openalex.org/W2765435638","https://openalex.org/W2098419840","https://openalex.org/W2140610743","https://openalex.org/W2121863912","https://openalex.org/W2986691431","https://openalex.org/W2152913847","https://openalex.org/W1870848632"],"abstract_inverted_index":{"In":[0],"this":[1],"work":[2],"we":[3],"focus":[4],"on":[5,91],"reducing":[6],"the":[7,13,22,33,62,65,83,101,110,127,131,147],"simultaneous":[8,58],"switching":[9,59],"noise":[10,60],"located":[11],"in":[12,64,94,130,155],"frequency":[14,27,66,128],"band":[15,28,35,134],"from":[16,138],"DC":[17],"up":[18,141],"to":[19,31,43,55,124,142],"half":[20],"of":[21,36,158,162],"digital":[23],"clock":[24,63],"frequency.":[25],"This":[26],"is":[29,42,104,152],"assumed":[30],"be":[32,136],"signal":[34,133],"an":[37,153],"analog":[38,132],"circuit.":[39],"The":[40,150],"idea":[41],"use":[44,69],"circuits":[45],"that":[46],"have":[47,88],"as":[48,53],"periodic":[49],"power":[50,156],"supply":[51],"currents":[52],"possible":[54],"obtain":[56],"low":[57],"below":[61],"domain.":[67],"We":[68],"precharged":[70],"differential":[71],"cascode":[72],"switch":[73],"logic":[74,116],"together":[75,117],"with":[76,106,113,118],"a":[77,95,119,160,165],"novel":[78,102],"D":[79,121],"flip-flop.":[80,122],"To":[81],"evaluate":[82],"method":[84,108],"two":[85],"pipelined":[86],"adders":[87],"been":[89],"implemented":[90,105],"transistor":[92,167],"level":[93],"0.13":[96],"mum":[97],"CMOS":[98,115],"technology,":[99],"where":[100],"circuit":[103,112],"our":[107],"and":[109,164],"reference":[111],"static":[114],"TSPC":[120],"According":[123],"simulation":[125],"results,":[126],"components":[129],"can":[135],"attenuated":[137],"10":[139],"dB":[140,144],"17":[143],"when":[145],"using":[146],"proposed":[148],"method.":[149],"cost":[151],"increase":[154],"consumption":[157],"almost":[159],"factor":[161],"three":[163],"higher":[166],"count.":[168]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
