{"id":"https://openalex.org/W2120793435","doi":"https://doi.org/10.1109/ecctd.2007.4529544","title":"Relating Cellular Non-linear Networks to Threshold Logic and Single Instruction Multiple Data computing models","display_name":"Relating Cellular Non-linear Networks to Threshold Logic and Single Instruction Multiple Data computing models","publication_year":2007,"publication_date":"2007-08-01","ids":{"openalex":"https://openalex.org/W2120793435","doi":"https://doi.org/10.1109/ecctd.2007.4529544","mag":"2120793435"},"language":"en","primary_location":{"id":"doi:10.1109/ecctd.2007.4529544","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2007.4529544","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 18th European Conference on Circuit Theory and Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077550469","display_name":"V.M. Brea","orcid":"https://orcid.org/0000-0003-0078-0425"},"institutions":[{"id":"https://openalex.org/I200284239","display_name":"Universidade de Santiago de Compostela","ror":"https://ror.org/030eybx10","country_code":"ES","type":"education","lineage":["https://openalex.org/I200284239"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"V.M. Brea","raw_affiliation_strings":["Departamento de Electronica e Computacon, Universidade de Santiago de Compostela, Santiago de Compostela, Spain","Dept. de Electron. e Comput., Univ. de Santiago de Compostela, Santiago de Compostela"],"affiliations":[{"raw_affiliation_string":"Departamento de Electronica e Computacon, Universidade de Santiago de Compostela, Santiago de Compostela, Spain","institution_ids":["https://openalex.org/I200284239"]},{"raw_affiliation_string":"Dept. de Electron. e Comput., Univ. de Santiago de Compostela, Santiago de Compostela","institution_ids":["https://openalex.org/I200284239"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052855358","display_name":"Mika Laiho","orcid":"https://orcid.org/0000-0002-3794-0800"},"institutions":[{"id":"https://openalex.org/I155660961","display_name":"University of Turku","ror":"https://ror.org/05vghhr25","country_code":"FI","type":"education","lineage":["https://openalex.org/I155660961"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"M. Laiho","raw_affiliation_strings":["Departamento de Electronica e Computacon, Universidad de Santiage de Compostela, Turku, Finland","Microelectronics Laboratory, University of Turku, Lemminkaisenkatu 14-18, 20540, Finland"],"affiliations":[{"raw_affiliation_string":"Departamento de Electronica e Computacon, Universidad de Santiage de Compostela, Turku, Finland","institution_ids":["https://openalex.org/I155660961"]},{"raw_affiliation_string":"Microelectronics Laboratory, University of Turku, Lemminkaisenkatu 14-18, 20540, Finland","institution_ids":["https://openalex.org/I155660961"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070182357","display_name":"Natalia A. Fernandez","orcid":null},"institutions":[{"id":"https://openalex.org/I200284239","display_name":"Universidade de Santiago de Compostela","ror":"https://ror.org/030eybx10","country_code":"ES","type":"education","lineage":["https://openalex.org/I200284239"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"N.A. Fernandez","raw_affiliation_strings":["Departamento de Electronica e Computacon, Universidade de Santiago de Compostela, Santiago de Compostela, Spain","Departamento de Electr\u00f3nica e Computaci\u00f3n, Universidade de Santiago de Compostela, E-15782, Spain"],"affiliations":[{"raw_affiliation_string":"Departamento de Electronica e Computacon, Universidade de Santiago de Compostela, Santiago de Compostela, Spain","institution_ids":["https://openalex.org/I200284239"]},{"raw_affiliation_string":"Departamento de Electr\u00f3nica e Computaci\u00f3n, Universidade de Santiago de Compostela, E-15782, Spain","institution_ids":["https://openalex.org/I200284239"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038944203","display_name":"A. Paasio","orcid":"https://orcid.org/0000-0003-2543-7391"},"institutions":[{"id":"https://openalex.org/I155660961","display_name":"University of Turku","ror":"https://ror.org/05vghhr25","country_code":"FI","type":"education","lineage":["https://openalex.org/I155660961"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"A. Paasio","raw_affiliation_strings":["Departamento de Electronica e Computacon, Universidad de Santiage de Compostela, Turku, Finland","Microelectronics Laboratory, University of Turku, Lemminkaisenkatu 14-18, 20540, Finland"],"affiliations":[{"raw_affiliation_string":"Departamento de Electronica e Computacon, Universidad de Santiage de Compostela, Turku, Finland","institution_ids":["https://openalex.org/I155660961"]},{"raw_affiliation_string":"Microelectronics Laboratory, University of Turku, Lemminkaisenkatu 14-18, 20540, Finland","institution_ids":["https://openalex.org/I155660961"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041970396","display_name":"D. Cabello","orcid":"https://orcid.org/0000-0002-4859-2899"},"institutions":[{"id":"https://openalex.org/I200284239","display_name":"Universidade de Santiago de Compostela","ror":"https://ror.org/030eybx10","country_code":"ES","type":"education","lineage":["https://openalex.org/I200284239"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"D. Cabello","raw_affiliation_strings":["Departamento de Electronica e Computacon, Universidade de Santiago de Compostela, Santiago de Compostela, Spain","Departamento de Electr\u00f3nica e Computaci\u00f3n, Universidade de Santiago de Compostela, E-15782, Spain"],"affiliations":[{"raw_affiliation_string":"Departamento de Electronica e Computacon, Universidade de Santiago de Compostela, Santiago de Compostela, Spain","institution_ids":["https://openalex.org/I200284239"]},{"raw_affiliation_string":"Departamento de Electr\u00f3nica e Computaci\u00f3n, Universidade de Santiago de Compostela, E-15782, Spain","institution_ids":["https://openalex.org/I200284239"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5077550469"],"corresponding_institution_ids":["https://openalex.org/I200284239"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.15363911,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"34","issue":null,"first_page":"92","last_page":"95"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/simd","display_name":"SIMD","score":0.9432298541069031},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8257603645324707},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6581754684448242},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.554885983467102},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5334435105323792},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5090136528015137},{"id":"https://openalex.org/keywords/binary-number","display_name":"Binary number","score":0.4877484440803528},{"id":"https://openalex.org/keywords/parallel-processing","display_name":"Parallel processing","score":0.4849553108215332},{"id":"https://openalex.org/keywords/image-processing","display_name":"Image processing","score":0.46807536482810974},{"id":"https://openalex.org/keywords/model-of-computation","display_name":"Model of computation","score":0.44527488946914673},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.41070181131362915},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.39487096667289734},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.36899083852767944},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.34251096844673157},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2904282808303833},{"id":"https://openalex.org/keywords/image","display_name":"Image (mathematics)","score":0.23592177033424377},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.1834125816822052},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.1566459834575653},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.15092715620994568},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08485385775566101}],"concepts":[{"id":"https://openalex.org/C150552126","wikidata":"https://www.wikidata.org/wiki/Q339387","display_name":"SIMD","level":2,"score":0.9432298541069031},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8257603645324707},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6581754684448242},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.554885983467102},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5334435105323792},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5090136528015137},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.4877484440803528},{"id":"https://openalex.org/C106515295","wikidata":"https://www.wikidata.org/wiki/Q26806595","display_name":"Parallel processing","level":2,"score":0.4849553108215332},{"id":"https://openalex.org/C9417928","wikidata":"https://www.wikidata.org/wiki/Q1070689","display_name":"Image processing","level":3,"score":0.46807536482810974},{"id":"https://openalex.org/C184596265","wikidata":"https://www.wikidata.org/wiki/Q2651576","display_name":"Model of computation","level":3,"score":0.44527488946914673},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.41070181131362915},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.39487096667289734},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.36899083852767944},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.34251096844673157},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2904282808303833},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.23592177033424377},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.1834125816822052},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.1566459834575653},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.15092715620994568},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08485385775566101}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ecctd.2007.4529544","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2007.4529544","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 18th European Conference on Circuit Theory and Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320326655","display_name":"Xunta de Galicia","ror":"https://ror.org/0181xnw06"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W1552895118","https://openalex.org/W1570173134","https://openalex.org/W1615879060","https://openalex.org/W1831098980","https://openalex.org/W1964031104","https://openalex.org/W2009832491","https://openalex.org/W2013339404","https://openalex.org/W2029343309","https://openalex.org/W2031577728","https://openalex.org/W2033279368","https://openalex.org/W2051518172","https://openalex.org/W2051540015","https://openalex.org/W2057127289","https://openalex.org/W2083770087","https://openalex.org/W2084192127","https://openalex.org/W2097988027","https://openalex.org/W2101313534","https://openalex.org/W2117148079","https://openalex.org/W2118572719","https://openalex.org/W2129816731","https://openalex.org/W2130416988","https://openalex.org/W2139740037","https://openalex.org/W2139886987","https://openalex.org/W2155296713","https://openalex.org/W2159448186","https://openalex.org/W2162093284","https://openalex.org/W2163288878","https://openalex.org/W2467244262","https://openalex.org/W2610639187","https://openalex.org/W4205749273","https://openalex.org/W4246475812","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W2099629705","https://openalex.org/W2234221250","https://openalex.org/W2065177255","https://openalex.org/W2371903265","https://openalex.org/W2013845618","https://openalex.org/W2156571376","https://openalex.org/W1576657130","https://openalex.org/W1667038987","https://openalex.org/W2006445609","https://openalex.org/W2096870795"],"abstract_inverted_index":{"This":[0],"paper":[1,64,77],"examines":[2],"three":[3,79,84],"apparently":[4],"different":[5],"computing":[6,85],"models,":[7],"namely,":[8],"threshold":[9],"logic":[10],"(TL),":[11],"cellular":[12],"nonlinear":[13],"networks":[14],"(CNN)":[15],"and":[16,32],"single":[17],"instruction":[18],"multiple":[19],"data":[20,48],"(SIMD).":[21],"TL":[22,132],"is":[23,65],"an":[24,139],"area":[25],"of":[26,56,62,70,101,113],"interest":[27],"in":[28,39],"modern":[29],"VLSI":[30],"design":[31],"computational":[33],"neuroscience.":[34],"CNNs":[35,108],"are":[36,98,135],"mainly":[37],"employed":[38],"image":[40,92],"processing.":[41,93],"Conventional":[42],"SIMD":[43,102,121],"architectures":[44],"aim":[45],"at":[46],"exploiting":[47],"parallelism":[49],"to":[50,67,137,141,147],"speed":[51],"up":[52],"the":[53,68,76,83],"execution":[54],"time":[55],"computation":[57],"intensive":[58],"algorithms.":[59],"The":[60],"scope":[61],"this":[63,74],"limited":[66],"processing":[69,122],"binary":[71,91,143],"images.":[72],"Within":[73],"scope,":[75],"conveys":[78],"main":[80],"conclusions.":[81],"First,":[82],"models":[86],"can":[87],"be":[88,138],"used":[89],"for":[90,128],"Second,":[94],"not":[95],"only":[96],"2D-CNNs":[97],"a":[99,110,118,151],"sub-class":[100],"architectures,":[103],"but":[104],"also":[105],"synchronous":[106],"2D-":[107,144],"with":[109,124,150],"reduced":[111],"set":[112],"coefficient":[114],"circuits":[115],"act":[116],"as":[117],"classical":[119],"1-bit":[120],"element":[123],"NEWS":[125],"(North-East-West-":[126],"South)":[127],"nearest-neighbor":[129],"communications.":[130],"Third,":[131],"gates":[133],"(TLGs)":[134],"proved":[136],"alternative":[140],"implement":[142],"CNNs,":[145],"leading":[146],"on-chip":[148],"solutions":[149],"very":[152],"high":[153],"performance.":[154]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}