{"id":"https://openalex.org/W1580716460","doi":"https://doi.org/10.1109/ecctd.2005.1523109","title":"Finite impulse response filter banks realized using switched capacitor technique","display_name":"Finite impulse response filter banks realized using switched capacitor technique","publication_year":2006,"publication_date":"2006-10-11","ids":{"openalex":"https://openalex.org/W1580716460","doi":"https://doi.org/10.1109/ecctd.2005.1523109","mag":"1580716460"},"language":"en","primary_location":{"id":"doi:10.1109/ecctd.2005.1523109","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2005.1523109","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088770647","display_name":"Rafa\u0142 D\u0142ugosz","orcid":"https://orcid.org/0000-0002-9153-5072"},"institutions":[{"id":"https://openalex.org/I46597724","display_name":"Pozna\u0144 University of Technology","ror":"https://ror.org/00p7p3302","country_code":"PL","type":"education","lineage":["https://openalex.org/I46597724"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"R. Dlugosz","raw_affiliation_strings":["Institute of Control and System Engineering, ul., Poznan University of Technology, Poznan, Poland","[Inst. of Control & Syst. Eng., Poznan Univ. of Technol., Poland]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Control and System Engineering, ul., Poznan University of Technology, Poznan, Poland","institution_ids":["https://openalex.org/I46597724"]},{"raw_affiliation_string":"[Inst. of Control & Syst. Eng., Poznan Univ. of Technol., Poland]","institution_ids":["https://openalex.org/I46597724"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010451414","display_name":"Pawe\u0142 Paw\u0142owski","orcid":"https://orcid.org/0000-0001-5373-5148"},"institutions":[{"id":"https://openalex.org/I46597724","display_name":"Pozna\u0144 University of Technology","ror":"https://ror.org/00p7p3302","country_code":"PL","type":"education","lineage":["https://openalex.org/I46597724"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"P. Pawlowski","raw_affiliation_strings":["[Inst. of Control & Syst. Eng., Poznan Univ. of Technol., Poland]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"[Inst. of Control & Syst. Eng., Poznan Univ. of Technol., Poland]","institution_ids":["https://openalex.org/I46597724"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101619455","display_name":"Adam D\u0105browski","orcid":"https://orcid.org/0000-0002-9385-6080"},"institutions":[{"id":"https://openalex.org/I46597724","display_name":"Pozna\u0144 University of Technology","ror":"https://ror.org/00p7p3302","country_code":"PL","type":"education","lineage":["https://openalex.org/I46597724"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"A. Dabrowski","raw_affiliation_strings":["Institute of Control and System Engineering, ul., Poznan University of Technology, Poznan, Poland","[Inst. of Control & Syst. Eng., Poznan Univ. of Technol., Poland]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Control and System Engineering, ul., Poznan University of Technology, Poznan, Poland","institution_ids":["https://openalex.org/I46597724"]},{"raw_affiliation_string":"[Inst. of Control & Syst. Eng., Poznan Univ. of Technol., Poland]","institution_ids":["https://openalex.org/I46597724"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I46597724"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.0618515,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"3","issue":null,"first_page":"257","last_page":"260"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/butterworth-filter","display_name":"Butterworth filter","score":0.5796148777008057},{"id":"https://openalex.org/keywords/filter-design","display_name":"Filter design","score":0.5750077962875366},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5655597448348999},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.5637148022651672},{"id":"https://openalex.org/keywords/filter-bank","display_name":"Filter bank","score":0.5019245147705078},{"id":"https://openalex.org/keywords/active-filter","display_name":"Active filter","score":0.4981381893157959},{"id":"https://openalex.org/keywords/digital-filter","display_name":"Digital filter","score":0.48923826217651367},{"id":"https://openalex.org/keywords/low-pass-filter","display_name":"Low-pass filter","score":0.4865831136703491},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4782504141330719},{"id":"https://openalex.org/keywords/switched-capacitor","display_name":"Switched capacitor","score":0.4718337655067444},{"id":"https://openalex.org/keywords/voltage-controlled-filter","display_name":"Voltage-controlled filter","score":0.4698673188686371},{"id":"https://openalex.org/keywords/finite-impulse-response","display_name":"Finite impulse response","score":0.46305060386657715},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.397206574678421},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3839818835258484},{"id":"https://openalex.org/keywords/prototype-filter","display_name":"Prototype filter","score":0.3607032299041748},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2947275638580322},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.14937728643417358}],"concepts":[{"id":"https://openalex.org/C70757512","wikidata":"https://www.wikidata.org/wiki/Q1018162","display_name":"Butterworth filter","level":5,"score":0.5796148777008057},{"id":"https://openalex.org/C22597639","wikidata":"https://www.wikidata.org/wiki/Q5449227","display_name":"Filter design","level":3,"score":0.5750077962875366},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5655597448348999},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.5637148022651672},{"id":"https://openalex.org/C100515483","wikidata":"https://www.wikidata.org/wiki/Q3268235","display_name":"Filter bank","level":3,"score":0.5019245147705078},{"id":"https://openalex.org/C85899133","wikidata":"https://www.wikidata.org/wiki/Q557211","display_name":"Active filter","level":3,"score":0.4981381893157959},{"id":"https://openalex.org/C36390408","wikidata":"https://www.wikidata.org/wiki/Q1163067","display_name":"Digital filter","level":3,"score":0.48923826217651367},{"id":"https://openalex.org/C44682112","wikidata":"https://www.wikidata.org/wiki/Q918242","display_name":"Low-pass filter","level":3,"score":0.4865831136703491},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4782504141330719},{"id":"https://openalex.org/C103357873","wikidata":"https://www.wikidata.org/wiki/Q572656","display_name":"Switched capacitor","level":4,"score":0.4718337655067444},{"id":"https://openalex.org/C126955663","wikidata":"https://www.wikidata.org/wiki/Q1638353","display_name":"Voltage-controlled filter","level":5,"score":0.4698673188686371},{"id":"https://openalex.org/C198386975","wikidata":"https://www.wikidata.org/wiki/Q117785","display_name":"Finite impulse response","level":2,"score":0.46305060386657715},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.397206574678421},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3839818835258484},{"id":"https://openalex.org/C175742284","wikidata":"https://www.wikidata.org/wiki/Q1415537","display_name":"Prototype filter","level":4,"score":0.3607032299041748},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2947275638580322},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.14937728643417358}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ecctd.2005.1523109","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2005.1523109","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8399999737739563,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W621177297","https://openalex.org/W1481646516","https://openalex.org/W2018235278","https://openalex.org/W2073920767","https://openalex.org/W2135116380","https://openalex.org/W2172219606","https://openalex.org/W2468925018","https://openalex.org/W3102918282","https://openalex.org/W6654994294","https://openalex.org/W6720180481"],"related_works":["https://openalex.org/W2132465642","https://openalex.org/W2323335032","https://openalex.org/W2150714587","https://openalex.org/W4385692266","https://openalex.org/W2065462772","https://openalex.org/W4245877442","https://openalex.org/W1492592725","https://openalex.org/W2481624947","https://openalex.org/W2142603601","https://openalex.org/W2988227767"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"we":[3],"present":[4],"a":[5,60,91,101,131],"conception":[6],"of":[7,47,70,106,126,133],"the":[8,17,32,48,68,71,95,111,123,127,134],"finite":[9],"impulse":[10],"response":[11,98],"(FIR)":[12],"filter":[13,24,52,62,72,93,102],"banks":[14],"realized":[15],"using":[16],"switched-capacitor":[18],"(SC)":[19],"rotator":[20],"architecture.":[21],"The":[22,78],"illustrative":[23],"bank":[25,103],"has":[26,114],"been":[27,54,115],"designed":[28,50,79],"and":[29,100,130],"fabricated":[30],"in":[31,56,83,110],"CMOS":[33],"0.35":[34],"/spl":[35],"mu/m":[36],"technology.":[37],"Its":[38],"main":[39],"advantage":[40],"is":[41],"simplicity,":[42],"as":[43],"only":[44],"few":[45],"modifications":[46,65],"initially":[49],"single":[51,92],"had":[53],"necessary":[55],"order":[57],"to":[58,87],"realize":[59],"QMF":[61],"bank.":[63],"These":[64],"changed":[66],"neither":[67],"area":[69],"layout":[73],"nor":[74],"its":[75],"power":[76],"consumption.":[77],"chip":[80],"can":[81],"operate":[82],"two":[84,108],"modes":[85,109],"easy":[86],"switch":[88],"between":[89,119],"them:":[90],"with":[94],"programmable":[96],"frequency":[97],"mode":[99],"mode.":[104],"Realization":[105],"these":[107],"same":[112],"circuit":[113],"possible,":[116],"because":[117],"switching":[118],"them":[120],"encompasses":[121],"merely":[122],"digital":[124],"part":[125],"control":[128],"system":[129],"subset":[132],"clock":[135],"signals.":[136]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
