{"id":"https://openalex.org/W1505241952","doi":"https://doi.org/10.1109/ecctd.2005.1523100","title":"Optimized design of ECL gates with a power constraint","display_name":"Optimized design of ECL gates with a power constraint","publication_year":2006,"publication_date":"2006-10-11","ids":{"openalex":"https://openalex.org/W1505241952","doi":"https://doi.org/10.1109/ecctd.2005.1523100","mag":"1505241952"},"language":"en","primary_location":{"id":"doi:10.1109/ecctd.2005.1523100","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2005.1523100","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078615947","display_name":"Alfio Dario Grasso","orcid":"https://orcid.org/0000-0002-5707-9683"},"institutions":[{"id":"https://openalex.org/I39063666","display_name":"University of Catania","ror":"https://ror.org/03a64bh57","country_code":"IT","type":"education","lineage":["https://openalex.org/I39063666"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"A.D. Grasso","raw_affiliation_strings":["Dipartimento di Ingegneria Elettrica Elettronica e dei Sistemi, Universita Catania, Italy","DIFES, Catania Univ., Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Elettrica Elettronica e dei Sistemi, Universita Catania, Italy","institution_ids":["https://openalex.org/I39063666"]},{"raw_affiliation_string":"DIFES, Catania Univ., Italy","institution_ids":["https://openalex.org/I39063666"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044422028","display_name":"G. Palumbo","orcid":"https://orcid.org/0000-0002-8011-8660"},"institutions":[{"id":"https://openalex.org/I39063666","display_name":"University of Catania","ror":"https://ror.org/03a64bh57","country_code":"IT","type":"education","lineage":["https://openalex.org/I39063666"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G. Palumbo","raw_affiliation_strings":["Dipartimento di Ingegneria Elettrica Elettronica e dei Sistemi, Universita Catania, Italy","DIFES, Catania Univ., Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Elettrica Elettronica e dei Sistemi, Universita Catania, Italy","institution_ids":["https://openalex.org/I39063666"]},{"raw_affiliation_string":"DIFES, Catania Univ., Italy","institution_ids":["https://openalex.org/I39063666"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5078615947"],"corresponding_institution_ids":["https://openalex.org/I39063666"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.0324901,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"3","issue":null,"first_page":"221","last_page":"224"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.8529882431030273},{"id":"https://openalex.org/keywords/emitter-coupled-logic","display_name":"Emitter-coupled logic","score":0.8524723052978516},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.7035651803016663},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.6237298846244812},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5836374759674072},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5782797932624817},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5745633244514465},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.5728630423545837},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5505526065826416},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5504527688026428},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.41123878955841064},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3251960873603821},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3043925166130066},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2845587730407715},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.26979368925094604},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.22601598501205444},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22521868348121643},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.21392962336540222},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.1756414771080017}],"concepts":[{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.8529882431030273},{"id":"https://openalex.org/C11644886","wikidata":"https://www.wikidata.org/wiki/Q173552","display_name":"Emitter-coupled logic","level":5,"score":0.8524723052978516},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.7035651803016663},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.6237298846244812},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5836374759674072},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5782797932624817},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5745633244514465},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.5728630423545837},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5505526065826416},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5504527688026428},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.41123878955841064},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3251960873603821},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3043925166130066},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2845587730407715},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.26979368925094604},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.22601598501205444},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22521868348121643},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.21392962336540222},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.1756414771080017},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ecctd.2005.1523100","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecctd.2005.1523100","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7699999809265137,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1595570256","https://openalex.org/W2049416769","https://openalex.org/W2057309670","https://openalex.org/W2095875220","https://openalex.org/W2124492065","https://openalex.org/W2163977372","https://openalex.org/W2169859839"],"related_works":["https://openalex.org/W2095875220","https://openalex.org/W2071491930","https://openalex.org/W2154325711","https://openalex.org/W2900863455","https://openalex.org/W3211084114","https://openalex.org/W1966891534","https://openalex.org/W4239403158","https://openalex.org/W2035475131","https://openalex.org/W2548569671","https://openalex.org/W1505241952"],"abstract_inverted_index":{"A":[0],"design":[1],"strategy":[2,71],"for":[3,41],"the":[4,7,47,58,62],"optimization":[5,25],"of":[6,10,31,38,57,95],"propagation":[8],"delay":[9],"emitter":[11],"coupled":[12],"logic":[13],"(ECL)":[14],"gates":[15],"when":[16,34],"a":[17,35,78,83,90],"power":[18],"constraint":[19],"is":[20,22,26,50,55,72],"present":[21],"discussed.":[23],"The":[24,52,69],"carried":[27],"out":[28],"in":[29],"terms":[30],"bias":[32],"currents":[33],"maximum":[36],"level":[37],"total":[39],"current":[40],"each":[42],"gate,":[43],"much":[44],"lower":[45],"than":[46],"optimum":[48],"one,":[49],"available.":[51],"proposed":[53,70],"approach":[54,64],"independent":[56],"process":[59,85],"used,":[60],"avoiding":[61],"trial-and-error":[63],"based":[65],"on":[66,77],"time-consuming":[67],"simulations.":[68],"validated":[73],"by":[74],"SPICE":[75],"simulations":[76],"two":[79],"input":[80],"multiplexer,":[81],"using":[82],"bipolar":[84],"whose":[86],"npn":[87],"transistor":[88],"has":[89],"transition":[91],"frequency":[92],"f/sub":[93],"T/":[94],"20":[96],"GHz.":[97]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
