{"id":"https://openalex.org/W3094426418","doi":"https://doi.org/10.1109/ecai50035.2020.9223238","title":"FPGA Implementation of a SD Card Controller using SPI communication","display_name":"FPGA Implementation of a SD Card Controller using SPI communication","publication_year":2020,"publication_date":"2020-06-01","ids":{"openalex":"https://openalex.org/W3094426418","doi":"https://doi.org/10.1109/ecai50035.2020.9223238","mag":"3094426418"},"language":"en","primary_location":{"id":"doi:10.1109/ecai50035.2020.9223238","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecai50035.2020.9223238","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 12th International Conference on Electronics, Computers and Artificial Intelligence (ECAI)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5046583296","display_name":"Dumitrel Catalin Costache","orcid":null},"institutions":[{"id":"https://openalex.org/I61641377","display_name":"Universitatea Na\u021bional\u0103 de \u0218tiin\u021b\u0103 \u0219i Tehnologie Politehnica Bucure\u0219ti","ror":"https://ror.org/0558j5q12","country_code":"RO","type":"education","lineage":["https://openalex.org/I61641377"]}],"countries":["RO"],"is_corresponding":false,"raw_author_name":"Dumitrel Catalin Costache","raw_affiliation_strings":["Faculty of Electronics, Telecommunications and Information Technology, University Politehnica of Bucharest, Romania"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Electronics, Telecommunications and Information Technology, University Politehnica of Bucharest, Romania","institution_ids":["https://openalex.org/I61641377"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112193055","display_name":"Lucian Andrei Peri\u015foar\u0103","orcid":"https://orcid.org/0000-0002-2222-1475"},"institutions":[{"id":"https://openalex.org/I61641377","display_name":"Universitatea Na\u021bional\u0103 de \u0218tiin\u021b\u0103 \u0219i Tehnologie Politehnica Bucure\u0219ti","ror":"https://ror.org/0558j5q12","country_code":"RO","type":"education","lineage":["https://openalex.org/I61641377"]}],"countries":["RO"],"is_corresponding":false,"raw_author_name":"Lucian Andrei Perisoara","raw_affiliation_strings":["Faculty of Electronics, Telecommunications and Information Technology, University Politehnica of Bucharest, Romania"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Electronics, Telecommunications and Information Technology, University Politehnica of Bucharest, Romania","institution_ids":["https://openalex.org/I61641377"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006853945","display_name":"Adriana Florescu","orcid":"https://orcid.org/0000-0002-0519-8437"},"institutions":[{"id":"https://openalex.org/I61641377","display_name":"Universitatea Na\u021bional\u0103 de \u0218tiin\u021b\u0103 \u0219i Tehnologie Politehnica Bucure\u0219ti","ror":"https://ror.org/0558j5q12","country_code":"RO","type":"education","lineage":["https://openalex.org/I61641377"]}],"countries":["RO"],"is_corresponding":false,"raw_author_name":"Adriana Florescu","raw_affiliation_strings":["Faculty of Electronics, Telecommunications and Information Technology, University Politehnica of Bucharest, Romania"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Electronics, Telecommunications and Information Technology, University Politehnica of Bucharest, Romania","institution_ids":["https://openalex.org/I61641377"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I61641377"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.9940999746322632,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.9252981543540955},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7863196134567261},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.738013505935669},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7023938894271851},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.6125892400741577},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.513782799243927},{"id":"https://openalex.org/keywords/protocol","display_name":"Protocol (science)","score":0.48928186297416687},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.4679590165615082},{"id":"https://openalex.org/keywords/communications-protocol","display_name":"Communications protocol","score":0.42031654715538025},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.4123145341873169},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.22709214687347412}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.9252981543540955},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7863196134567261},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.738013505935669},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7023938894271851},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.6125892400741577},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.513782799243927},{"id":"https://openalex.org/C2780385302","wikidata":"https://www.wikidata.org/wiki/Q367158","display_name":"Protocol (science)","level":3,"score":0.48928186297416687},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.4679590165615082},{"id":"https://openalex.org/C12269588","wikidata":"https://www.wikidata.org/wiki/Q132364","display_name":"Communications protocol","level":2,"score":0.42031654715538025},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.4123145341873169},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.22709214687347412},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C142724271","wikidata":"https://www.wikidata.org/wiki/Q7208","display_name":"Pathology","level":1,"score":0.0},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0},{"id":"https://openalex.org/C204787440","wikidata":"https://www.wikidata.org/wiki/Q188504","display_name":"Alternative medicine","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ecai50035.2020.9223238","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecai50035.2020.9223238","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 12th International Conference on Electronics, Computers and Artificial Intelligence (ECAI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7099999785423279,"id":"https://metadata.un.org/sdg/4","display_name":"Quality Education"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1963993598","https://openalex.org/W2007124468","https://openalex.org/W2119929183","https://openalex.org/W2147836562","https://openalex.org/W2319737834"],"related_works":["https://openalex.org/W3004362061","https://openalex.org/W4297665406","https://openalex.org/W2364622490","https://openalex.org/W2383986884","https://openalex.org/W2356141508","https://openalex.org/W1735031787","https://openalex.org/W2749962643","https://openalex.org/W2390807153","https://openalex.org/W2110818533","https://openalex.org/W2042515040"],"abstract_inverted_index":{"The":[0,87,133,151],"Field":[1],"Programmable":[2],"Gate":[3],"Array":[4],"(FPGA)":[5],"devices":[6],"are":[7,52,58,138],"being":[8],"used":[9],"more":[10,157],"and":[11,60,71,79,107,136,160],"more,":[12],"especially":[13],"in":[14,23],"applications":[15],"that":[16,57,76,164],"require":[17],"real-time":[18],"data":[19,129],"processing,":[20],"for":[21,31,96],"example":[22],"communication":[24],"systems.":[25],"To":[26],"meet":[27],"the":[28,34,84,114,117,161,165],"memory":[29,36],"requirements":[30],"FPGA":[32,74,152],"systems,":[33],"onboard":[35],"can":[37,61,119,167],"be":[38,43,62],"used,":[39],"but":[40],"it":[41],"cannot":[42],"expanded":[44],"easily":[45],"by":[46],"adding":[47],"some":[48],"cards.":[49],"More":[50],"useful":[51],"Secure":[53],"Digital":[54],"(SD)":[55],"cards":[56,82,123,159],"detachable":[59],"replaced":[63],"easily.":[64],"In":[65],"this":[66],"paper,":[67],"we":[68],"have":[69],"designed":[70],"implemented":[72],"a":[73,93,125,141],"controller":[75,153],"allows":[77],"writing":[78],"reading":[80],"SD":[81,122,158],"using":[83,148],"SPI":[85,115],"protocol.":[86],"main":[88],"objective":[89],"is":[90],"to":[91,98,109],"provide":[92],"storage":[94,111],"solution":[95],"FPGAs,":[97],"store":[99],"large":[100,103],"files":[101],"on":[102,140],"capacity,":[104],"cheap,":[105],"portable":[106],"easy":[108],"use":[110],"devices.":[112],"Using":[113],"protocol,":[116],"system":[118,166],"access":[120],"multiple":[121],"with":[124,145,156],"minimum":[126],"usage":[127],"of":[128],"lines":[130],"from":[131],"FPGA.":[132],"hardware":[134],"design":[135],"implementation":[137],"developed":[139],"Xilinx":[142],"AC701":[143],"platform":[144],"Artix-7":[146],"FPGA,":[147],"VHDL":[149],"language.":[150],"was":[154],"tested":[155],"results":[162],"shown":[163],"run":[168],"without":[169],"errors.":[170]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}