{"id":"https://openalex.org/W2937596606","doi":"https://doi.org/10.1109/ecai.2018.8679099","title":"A Unified VLSI architecture for 1D IDCT and IDST based on pseudo-band correlations","display_name":"A Unified VLSI architecture for 1D IDCT and IDST based on pseudo-band correlations","publication_year":2018,"publication_date":"2018-06-01","ids":{"openalex":"https://openalex.org/W2937596606","doi":"https://doi.org/10.1109/ecai.2018.8679099","mag":"2937596606"},"language":"en","primary_location":{"id":"doi:10.1109/ecai.2018.8679099","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecai.2018.8679099","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 10th International Conference on Electronics, Computers and Artificial Intelligence (ECAI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009246558","display_name":"Doru Florin Chiper","orcid":"https://orcid.org/0000-0002-3322-4663"},"institutions":[{"id":"https://openalex.org/I4210108695","display_name":"Gheorghe Asachi Technical University of Ia\u0219i","ror":"https://ror.org/014zxnz40","country_code":"RO","type":"education","lineage":["https://openalex.org/I4210108695"]}],"countries":["RO"],"is_corresponding":true,"raw_author_name":"Doru Florin CHIPER","raw_affiliation_strings":["Technical University Gheorghe Asachi, Iasi, Romania"],"affiliations":[{"raw_affiliation_string":"Technical University Gheorghe Asachi, Iasi, Romania","institution_ids":["https://openalex.org/I4210108695"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050948290","display_name":"Laura Teodora Cotorobai","orcid":null},"institutions":[{"id":"https://openalex.org/I4210108695","display_name":"Gheorghe Asachi Technical University of Ia\u0219i","ror":"https://ror.org/014zxnz40","country_code":"RO","type":"education","lineage":["https://openalex.org/I4210108695"]}],"countries":["RO"],"is_corresponding":false,"raw_author_name":"Laura Teodora COTOROBAI","raw_affiliation_strings":["Technical University Gheorghe Asachi, Iasi, Romania"],"affiliations":[{"raw_affiliation_string":"Technical University Gheorghe Asachi, Iasi, Romania","institution_ids":["https://openalex.org/I4210108695"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5009246558"],"corresponding_institution_ids":["https://openalex.org/I4210108695"],"apc_list":null,"apc_paid":null,"fwci":0.1651,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.50301664,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11233","display_name":"Advanced Adaptive Filtering Techniques","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/2206","display_name":"Computational Mechanics"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7805353999137878},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6487802267074585},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5746239423751831},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5220218300819397},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5061516165733337},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.17556896805763245},{"id":"https://openalex.org/keywords/art","display_name":"Art","score":0.048667341470718384}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7805353999137878},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6487802267074585},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5746239423751831},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5220218300819397},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5061516165733337},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.17556896805763245},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.048667341470718384},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ecai.2018.8679099","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ecai.2018.8679099","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 10th International Conference on Electronics, Computers and Artificial Intelligence (ECAI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.4300000071525574}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1536599844","https://openalex.org/W1966904279","https://openalex.org/W1970975843","https://openalex.org/W1971118267","https://openalex.org/W1987995081","https://openalex.org/W2069216398","https://openalex.org/W2105613219","https://openalex.org/W2107115918","https://openalex.org/W2110790980","https://openalex.org/W2111431579","https://openalex.org/W2111513816","https://openalex.org/W2119985463","https://openalex.org/W2136930455","https://openalex.org/W2150242052","https://openalex.org/W2154807244","https://openalex.org/W2159478780","https://openalex.org/W2592499194","https://openalex.org/W6643042283"],"related_works":["https://openalex.org/W2383828164","https://openalex.org/W396164270","https://openalex.org/W1997145140","https://openalex.org/W4236512364","https://openalex.org/W2034384303","https://openalex.org/W2046094129","https://openalex.org/W4252688335","https://openalex.org/W1974303716","https://openalex.org/W1933802032","https://openalex.org/W804690729"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"an":[3,57],"efficient":[4,58],"unified":[5,42],"VLSI":[6,43,59,112],"architecture":[7,60,101],"for":[8],"the":[9,24,54,66,85,89,99],"computation":[10],"of":[11,80,88],"1-D":[12],"IDCT":[13],"and":[14,76,92,105],"IDST":[15],"that":[16,45],"have":[17],"been":[18,62],"reformulated":[19],"to":[20,49],"be":[21,47],"implemented":[22],"on":[23,39,65],"same":[25],"hardware":[26,74],"structure":[27],"with":[28,71,106],"a":[29,40,72,77,94,110],"minimum":[30],"modification":[31],"is":[32,37,102],"presented.":[33],"The":[34],"proposed":[35,55,100],"design":[36],"based":[38,64],"new":[41],"algorithm":[44,56],"can":[46],"used":[48],"compute":[50],"both":[51],"transforms.":[52],"Using":[53],"has":[61],"obtained":[63],"systolic":[67],"array":[68,91],"architectural":[69],"paradigm":[70],"low":[73,78,95],"complexity":[75],"number":[79],"I/O":[81,96],"channels":[82],"placed":[83],"at":[84],"two":[86],"ends":[87],"linear":[90],"having":[93],"bandwidth.":[97],"Moreover":[98],"modular,":[103],"regular":[104],"local":[107],"connection":[108],"favoring":[109],"good":[111],"implementation.":[113]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}