{"id":"https://openalex.org/W2418564214","doi":"https://doi.org/10.1109/dtis.2016.7483890","title":"A novel heterogeneous FPGA architecture based on memristor-transistor hybrid approach","display_name":"A novel heterogeneous FPGA architecture based on memristor-transistor hybrid approach","publication_year":2016,"publication_date":"2016-04-01","ids":{"openalex":"https://openalex.org/W2418564214","doi":"https://doi.org/10.1109/dtis.2016.7483890","mag":"2418564214"},"language":"en","primary_location":{"id":"doi:10.1109/dtis.2016.7483890","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dtis.2016.7483890","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088890905","display_name":"Umer Farooq","orcid":"https://orcid.org/0000-0002-5220-4908"},"institutions":[{"id":"https://openalex.org/I4210159731","display_name":"Laboratoire de Recherche en Informatique de Paris 6","ror":"https://ror.org/05krcen59","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I39804081","https://openalex.org/I4210159245","https://openalex.org/I4210159731"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Umer Farooq","raw_affiliation_strings":["SoC Department, LiP6, Paris, France"],"affiliations":[{"raw_affiliation_string":"SoC Department, LiP6, Paris, France","institution_ids":["https://openalex.org/I4210159731"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043625171","display_name":"Muhammad Khurram Bhatti","orcid":"https://orcid.org/0000-0002-1974-8268"},"institutions":[{"id":"https://openalex.org/I1323252656","display_name":"Information Technology University","ror":"https://ror.org/00ngv8j44","country_code":"PK","type":"education","lineage":["https://openalex.org/I1323252656"]}],"countries":["PK"],"is_corresponding":false,"raw_author_name":"M. Khurram Bhatti","raw_affiliation_strings":["Embedded Computing Lab, Information Technology University, Pakistan"],"affiliations":[{"raw_affiliation_string":"Embedded Computing Lab, Information Technology University, Pakistan","institution_ids":["https://openalex.org/I1323252656"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070648764","display_name":"M. Hassan Aslam","orcid":"https://orcid.org/0000-0002-7614-9157"},"institutions":[{"id":"https://openalex.org/I16076960","display_name":"COMSATS University Islamabad","ror":"https://ror.org/00nqqvk19","country_code":"PK","type":"education","lineage":["https://openalex.org/I16076960"]}],"countries":["PK"],"is_corresponding":false,"raw_author_name":"M. Hassan Aslam","raw_affiliation_strings":["COMSATS Institute of Information Technology - Attock Campus, Attock, Punjab, PK"],"affiliations":[{"raw_affiliation_string":"COMSATS Institute of Information Technology - Attock Campus, Attock, Punjab, PK","institution_ids":["https://openalex.org/I16076960"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5088890905"],"corresponding_institution_ids":["https://openalex.org/I4210159731"],"apc_list":null,"apc_paid":null,"fwci":0.1867,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.56783027,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"22","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9950000047683716,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8672605752944946},{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.64630126953125},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6285717487335205},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5995160341262817},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5923124551773071},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.4946272075176239},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4504675269126892},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4136490225791931},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3910816013813019},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.34453368186950684},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19364574551582336},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1881241798400879},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10664263367652893}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8672605752944946},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.64630126953125},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6285717487335205},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5995160341262817},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5923124551773071},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.4946272075176239},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4504675269126892},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4136490225791931},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3910816013813019},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.34453368186950684},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19364574551582336},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1881241798400879},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10664263367652893}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/dtis.2016.7483890","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dtis.2016.7483890","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)","raw_type":"proceedings-article"},{"id":"pmh:oai:sure.sunderland.ac.uk:16372","is_oa":false,"landing_page_url":"http://sure.sunderland.ac.uk/id/eprint/16372/","pdf_url":null,"source":{"id":"https://openalex.org/S4306402295","display_name":"Sunderland Repository (University of Sunderland)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I5728261","host_organization_name":"University of Sunderland","host_organization_lineage":["https://openalex.org/I5728261"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"PeerReviewed"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.44999998807907104,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1492116267","https://openalex.org/W1532559922","https://openalex.org/W1553214226","https://openalex.org/W1991973578","https://openalex.org/W2004782555","https://openalex.org/W2024060531","https://openalex.org/W2026429700","https://openalex.org/W2042525997","https://openalex.org/W2059441802","https://openalex.org/W2070608594","https://openalex.org/W2081729575","https://openalex.org/W2105011467","https://openalex.org/W2111756578","https://openalex.org/W2112181056","https://openalex.org/W2139580250","https://openalex.org/W2141071915","https://openalex.org/W2162651880","https://openalex.org/W2163031927","https://openalex.org/W2275304190","https://openalex.org/W2964151426","https://openalex.org/W4206262605","https://openalex.org/W6631737855"],"related_works":["https://openalex.org/W1485756991","https://openalex.org/W2376218453","https://openalex.org/W2110265185","https://openalex.org/W3146360095","https://openalex.org/W2018147837","https://openalex.org/W1612076744","https://openalex.org/W2184011203","https://openalex.org/W2129019972","https://openalex.org/W3164085601","https://openalex.org/W2984236338"],"abstract_inverted_index":{"Heterogeneous":[0],"Field":[1],"Programmable":[2],"Gate":[3],"Arrays":[4],"(FPGAs)":[5],"are":[6,74,86,115],"now":[7],"considered":[8],"a":[9,47,94],"practical":[10],"alternative":[11],"to":[12,19,27,61,90,148,154],"Application":[13],"Specific":[14],"Integrated":[15],"Circuits":[16],"(ASICs)":[17],"thanks":[18],"their":[20],"generalized":[21,95],"reconfigurable":[22],"nature":[23],"and":[24,36,76,104,117,121],"fast":[25],"time":[26],"market.":[28],"However,":[29],"the":[30,126],"area,":[31,141],"performance":[32],"gap":[33],"between":[34],"FPGAs":[35,124],"ASICs":[37],"is":[38,98],"still":[39],"quite":[40],"huge.":[41],"In":[42],"this":[43,79],"work,":[44],"we":[45],"propose":[46],"novel":[48],"memristor-transistor":[49],"hybrid":[50,68,84,133],"heterogeneous":[51,64,72,113,123],"FPGA":[52,73],"architecture":[53],"that":[54,83,131],"gives":[55],"better":[56],"area":[57,151],"results":[58],"as":[59],"compared":[60,89,153],"conventional":[62,122,155],"transistor-only":[63,91],"FPGA.":[65],"Memristor-transistor":[66],"based":[67],"building":[69],"blocks":[70,85],"of":[71],"designed":[75],"simulated":[77],"in":[78],"work.":[80],"Results":[81,129],"show":[82,130],"25%\u201360%":[87],"smaller":[88],"blocks.":[92],"Furthermore,":[93],"exploration":[96,110,127],"flow":[97],"also":[99],"proposed":[100,120,132],"where":[101],"open":[102],"source":[103],"indigenously":[105],"developed":[106],"tools":[107],"give":[108],"end-to-end":[109],"experience.":[111],"Ten":[112],"benchmarks":[114],"placed":[116],"routed":[118],"on":[119,135],"using":[125],"flow.":[128],"architecture,":[134],"average,":[136],"consumes":[137],"56%":[138],"less":[139,143],"logic":[140],"60%":[142],"routing":[144],"area;":[145],"thus":[146],"leading":[147],"59%":[149],"total":[150],"gain":[152],"architecture.":[156]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
