{"id":"https://openalex.org/W2410795002","doi":"https://doi.org/10.1109/dtis.2016.7483881","title":"MAC unit for reconfigurable systems using multi-operand adders with double carry-save encoding","display_name":"MAC unit for reconfigurable systems using multi-operand adders with double carry-save encoding","publication_year":2016,"publication_date":"2016-04-01","ids":{"openalex":"https://openalex.org/W2410795002","doi":"https://doi.org/10.1109/dtis.2016.7483881","mag":"2410795002"},"language":"en","primary_location":{"id":"doi:10.1109/dtis.2016.7483881","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dtis.2016.7483881","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038302966","display_name":"U\u011fur \u00c7ini","orcid":"https://orcid.org/0000-0002-9827-7993"},"institutions":[{"id":"https://openalex.org/I12387023","display_name":"Trakya University","ror":"https://ror.org/00xa0xn82","country_code":"TR","type":"education","lineage":["https://openalex.org/I12387023"]}],"countries":["TR"],"is_corresponding":true,"raw_author_name":"Ugur Cini","raw_affiliation_strings":["Electrical & Electronics Engineering, Trakya University, Editne, Turkey"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical & Electronics Engineering, Trakya University, Editne, Turkey","institution_ids":["https://openalex.org/I12387023"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017700426","display_name":"Olcay Kurt","orcid":null},"institutions":[{"id":"https://openalex.org/I12387023","display_name":"Trakya University","ror":"https://ror.org/00xa0xn82","country_code":"TR","type":"education","lineage":["https://openalex.org/I12387023"]}],"countries":["TR"],"is_corresponding":false,"raw_author_name":"Olcay Kurt","raw_affiliation_strings":["Institute of Natural and Applied Sciences, Trakya University, Edirne, Turkey"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Natural and Applied Sciences, Trakya University, Edirne, Turkey","institution_ids":["https://openalex.org/I12387023"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5038302966"],"corresponding_institution_ids":["https://openalex.org/I12387023"],"apc_list":null,"apc_paid":null,"fwci":0.186,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.56646557,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8585703372955322},{"id":"https://openalex.org/keywords/operand","display_name":"Operand","score":0.8193801641464233},{"id":"https://openalex.org/keywords/carry","display_name":"Carry (investment)","score":0.8092650771141052},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7225102186203003},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.6381707191467285},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5636390447616577},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.5286529660224915},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5166864395141602},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.5046044588088989},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.5020077228546143},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4884766638278961},{"id":"https://openalex.org/keywords/serial-binary-adder","display_name":"Serial binary adder","score":0.4851003885269165},{"id":"https://openalex.org/keywords/encoding","display_name":"Encoding (memory)","score":0.4698326289653778},{"id":"https://openalex.org/keywords/arithmetic-logic-unit","display_name":"Arithmetic logic unit","score":0.4278857409954071},{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.41243448853492737},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.20684820413589478},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.17911049723625183}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8585703372955322},{"id":"https://openalex.org/C55526617","wikidata":"https://www.wikidata.org/wiki/Q719375","display_name":"Operand","level":2,"score":0.8193801641464233},{"id":"https://openalex.org/C2776299755","wikidata":"https://www.wikidata.org/wiki/Q432449","display_name":"Carry (investment)","level":2,"score":0.8092650771141052},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7225102186203003},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.6381707191467285},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5636390447616577},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.5286529660224915},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5166864395141602},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.5046044588088989},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.5020077228546143},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4884766638278961},{"id":"https://openalex.org/C116206932","wikidata":"https://www.wikidata.org/wiki/Q7454686","display_name":"Serial binary adder","level":4,"score":0.4851003885269165},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.4698326289653778},{"id":"https://openalex.org/C100276221","wikidata":"https://www.wikidata.org/wiki/Q192903","display_name":"Arithmetic logic unit","level":2,"score":0.4278857409954071},{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.41243448853492737},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.20684820413589478},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.17911049723625183},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C10138342","wikidata":"https://www.wikidata.org/wiki/Q43015","display_name":"Finance","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dtis.2016.7483881","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dtis.2016.7483881","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5299999713897705,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W124596592","https://openalex.org/W2049910134","https://openalex.org/W2069381330","https://openalex.org/W2094665651","https://openalex.org/W2100563612","https://openalex.org/W2133562798","https://openalex.org/W2552956953","https://openalex.org/W2916844179","https://openalex.org/W6605094742","https://openalex.org/W6730338435","https://openalex.org/W7007630130"],"related_works":["https://openalex.org/W2558076308","https://openalex.org/W2357587666","https://openalex.org/W2162004439","https://openalex.org/W4285082868","https://openalex.org/W2288089334","https://openalex.org/W2374852146","https://openalex.org/W4380265034","https://openalex.org/W1929133780","https://openalex.org/W4294439455","https://openalex.org/W2152984054"],"abstract_inverted_index":{"In":[0,13,30],"this":[1],"work,":[2],"carry-free":[3],"redundant":[4,19,161],"arithmetic":[5,141,162],"based":[6,151,155,163],"fused":[7],"multiply-accumulate":[8,135],"(MAC)":[9],"units":[10,102],"are":[11,66,81,87,116],"designed.":[12],"the":[14,31,45,60,73,78,85,140],"first":[15],"design,":[16,33],"a":[17,34],"regular":[18],"carry-save":[20,28,50,91],"MAC":[21,101,156,164],"unit":[22],"is":[23,37],"designed":[24],"using":[25],"well":[26],"known":[27],"techniques.":[29],"second":[32],"hybrid":[35],"design":[36],"proposed":[38,54],"to":[39,71,131,147],"exploit":[40],"fast":[41],"carry":[42,159],"chains":[43,58],"of":[44,59,77],"FPGA":[46,61],"together":[47],"with":[48,106],"double":[49,90],"output":[51,109],"encoding.":[52],"The":[53,75,114,137],"scheme":[55],"exploits":[56],"fast-carry":[57],"structure,":[62],"and,":[63],"multi-operand":[64,79],"adders":[65,80],"divided":[67],"into":[68],"smaller":[69],"blocks":[70],"increase":[72],"performance.":[74],"outputs":[76],"not":[82],"merged":[83],"and":[84,126,158],"results":[86],"kept":[88],"in":[89,139],"format":[92],"where":[93],"extra":[94],"redundancy":[95],"reduces":[96],"critical":[97],"path":[98],"delay.":[99],"Designed":[100],"have":[103],"16\u00d716-bit":[104],"multiplier":[105,150,154],"40-digit":[107],"accumulate":[108],"for":[110],"recursive":[111],"multiply-add":[112],"operations.":[113],"designs":[115],"synthesized":[117],"on":[118],"Altera":[119],"<sup":[120],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[121],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">TM</sup>":[122],"Stratix":[123],"III":[124],"FPGAs":[125],"provide":[127],"superior":[128],"performance":[129,145],"compared":[130,146],"conventional":[132,148],"pipelined":[133,149],"carry-propagate":[134],"units.":[136],"fusion":[138],"structure":[142],"provides":[143],"best":[144],"structures,":[152],"hard":[153],"units,":[157],"free":[160],"structures":[165],"as":[166],"well.":[167]},"counts_by_year":[{"year":2024,"cited_by_count":3},{"year":2022,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2026-04-30T06:05:26.967640","created_date":"2025-10-10T00:00:00"}
