{"id":"https://openalex.org/W1979534964","doi":"https://doi.org/10.1109/dtis.2014.6850659","title":"A web EDA tool for the automatic generation of synthesizable VHDL architectures for a rapid design space exploration","display_name":"A web EDA tool for the automatic generation of synthesizable VHDL architectures for a rapid design space exploration","publication_year":2014,"publication_date":"2014-05-01","ids":{"openalex":"https://openalex.org/W1979534964","doi":"https://doi.org/10.1109/dtis.2014.6850659","mag":"1979534964"},"language":"en","primary_location":{"id":"doi:10.1109/dtis.2014.6850659","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dtis.2014.6850659","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006781417","display_name":"Minas Dasygenis","orcid":"https://orcid.org/0000-0002-2180-9752"},"institutions":[{"id":"https://openalex.org/I89506807","display_name":"University of Western Macedonia","ror":"https://ror.org/00a5pe906","country_code":"GR","type":"education","lineage":["https://openalex.org/I89506807"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Minas Dasygenis","raw_affiliation_strings":["Department of Informatics and Telecommunications Engineering, University of Western Macedonia, Kozani, Greece","Dept. of Inf. & Telecommun. Eng., Univ. of Western Macedonia, Kozani, Greece"],"affiliations":[{"raw_affiliation_string":"Department of Informatics and Telecommunications Engineering, University of Western Macedonia, Kozani, Greece","institution_ids":["https://openalex.org/I89506807"]},{"raw_affiliation_string":"Dept. of Inf. & Telecommun. Eng., Univ. of Western Macedonia, Kozani, Greece","institution_ids":["https://openalex.org/I89506807"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5006781417"],"corresponding_institution_ids":["https://openalex.org/I89506807"],"apc_list":null,"apc_paid":null,"fwci":2.7583,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.90065638,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"4627","issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.9853096008300781},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7899365425109863},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7335705757141113},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6522007584571838},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.5521470904350281},{"id":"https://openalex.org/keywords/generator","display_name":"Generator (circuit theory)","score":0.5506276488304138},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.5373920202255249},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.5135064721107483},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.49166232347488403},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.48767149448394775},{"id":"https://openalex.org/keywords/vhdl-ams","display_name":"VHDL-AMS","score":0.43473243713378906},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4192315638065338},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4167347550392151},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.41277772188186646},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.40854889154434204},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.35360562801361084},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3346136510372162},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.1689389944076538},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.09111139178276062}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.9853096008300781},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7899365425109863},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7335705757141113},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6522007584571838},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.5521470904350281},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.5506276488304138},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.5373920202255249},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.5135064721107483},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.49166232347488403},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.48767149448394775},{"id":"https://openalex.org/C2776513426","wikidata":"https://www.wikidata.org/wiki/Q2744740","display_name":"VHDL-AMS","level":4,"score":0.43473243713378906},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4192315638065338},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4167347550392151},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.41277772188186646},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.40854889154434204},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.35360562801361084},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3346136510372162},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.1689389944076538},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.09111139178276062},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dtis.2014.6850659","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dtis.2014.6850659","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W186834737","https://openalex.org/W1922832738","https://openalex.org/W2112432448","https://openalex.org/W2132089805","https://openalex.org/W2541283684","https://openalex.org/W6640194593"],"related_works":["https://openalex.org/W2498204369","https://openalex.org/W1557016741","https://openalex.org/W1586741485","https://openalex.org/W1967668957","https://openalex.org/W2543290882","https://openalex.org/W2162678295","https://openalex.org/W54894869","https://openalex.org/W2112319484","https://openalex.org/W2086925677","https://openalex.org/W2544421437"],"abstract_inverted_index":{"Design":[0],"space":[1],"exploration":[2],"of":[3,10,31,85],"new":[4],"circuit":[5],"methodologies":[6],"require":[7],"the":[8,18,29,83],"creation":[9],"models":[11],"in":[12],"hardware":[13],"description":[14],"languages":[15],"to":[16,60,64,74],"evaluate":[17,75],"characteristics":[19],"for":[20],"different":[21],"parameters,":[22],"a":[23,36,41],"time":[24],"consuming":[25],"process.":[26],"To":[27],"alleviate":[28],"burden":[30],"HDL":[32],"construction,":[33],"we":[34],"present":[35],"compact":[37],"netlist":[38,62,80],"format":[39],"and":[40,70],"web":[42],"tool":[43],"that":[44],"creates":[45],"syntactically":[46],"correct":[47],"VHDL":[48,68],"files.":[49],"The":[50],"designer":[51],"can":[52],"use":[53],"our":[54,86],"tool,":[55],"together":[56],"with":[57],"an":[58],"easy":[59],"create":[61,66],"generator,":[63],"quickly":[65],"multiple":[67],"files":[69],"skeleton":[71],"test":[72],"benches,":[73],"his":[76],"model.":[77],"Our":[78],"parametrized":[79],"generators":[81],"illustrate":[82],"efficiency":[84],"EDA":[87],"tool.":[88]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}