{"id":"https://openalex.org/W1992975559","doi":"https://doi.org/10.1109/dtis.2014.6850647","title":"Memristor based memories: Technology, design and test","display_name":"Memristor based memories: Technology, design and test","publication_year":2014,"publication_date":"2014-05-01","ids":{"openalex":"https://openalex.org/W1992975559","doi":"https://doi.org/10.1109/dtis.2014.6850647","mag":"1992975559"},"language":"en","primary_location":{"id":"doi:10.1109/dtis.2014.6850647","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dtis.2014.6850647","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 9th IEEE International Conference on Design &amp; Technology of Integrated Systems in Nanoscale Era (DTIS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005739146","display_name":"Said Hamdioui","orcid":"https://orcid.org/0000-0002-8961-0387"},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":true,"raw_author_name":"Said Hamdioui","raw_affiliation_strings":["Computer Engineering, Delft University of Technology, The Netherlands","Comput. Eng. Delft Univ. of Technol., Delft, Netherlands"],"affiliations":[{"raw_affiliation_string":"Computer Engineering, Delft University of Technology, The Netherlands","institution_ids":["https://openalex.org/I98358874"]},{"raw_affiliation_string":"Comput. Eng. Delft Univ. of Technol., Delft, Netherlands","institution_ids":["https://openalex.org/I98358874"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076568215","display_name":"H. Aziza","orcid":"https://orcid.org/0000-0002-8278-7462"},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I21491767","display_name":"Aix-Marseille Universit\u00e9","ror":"https://ror.org/035xkbk20","country_code":"FR","type":"education","lineage":["https://openalex.org/I21491767"]},{"id":"https://openalex.org/I4210112016","display_name":"Institut des Mat\u00e9riaux, de Micro\u00e9lectronique et des Nanosciences de Provence","ror":"https://ror.org/0238zyh04","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I143002897","https://openalex.org/I21491767","https://openalex.org/I3132279224","https://openalex.org/I4210098836","https://openalex.org/I4210112016"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Hassan Aziza","raw_affiliation_strings":["IM2NP, UMR CNRS, France","IM2NP, Aix-Marseille University, Marseille, France"],"affiliations":[{"raw_affiliation_string":"IM2NP, UMR CNRS, France","institution_ids":["https://openalex.org/I4210112016","https://openalex.org/I1294671590"]},{"raw_affiliation_string":"IM2NP, Aix-Marseille University, Marseille, France","institution_ids":["https://openalex.org/I21491767","https://openalex.org/I4210112016"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5008924272","display_name":"Georgios Ch. Sirakoulis","orcid":"https://orcid.org/0000-0001-8240-484X"},"institutions":[{"id":"https://openalex.org/I147962203","display_name":"Democritus University of Thrace","ror":"https://ror.org/03bfqnx40","country_code":"GR","type":"education","lineage":["https://openalex.org/I147962203"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Georgios Ch. Sirakoulis","raw_affiliation_strings":["Democritus University of Thrace, Greece","Democritus University of Thrace , Komotini, Greece"],"affiliations":[{"raw_affiliation_string":"Democritus University of Thrace, Greece","institution_ids":["https://openalex.org/I147962203"]},{"raw_affiliation_string":"Democritus University of Thrace , Komotini, Greece","institution_ids":["https://openalex.org/I147962203"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5005739146"],"corresponding_institution_ids":["https://openalex.org/I98358874"],"apc_list":null,"apc_paid":null,"fwci":4.4699,"has_fulltext":false,"cited_by_count":55,"citation_normalized_percentile":{"value":0.94999548,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.8484668731689453},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.7689589262008667},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6500670909881592},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.6082121133804321},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5907526612281799},{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.5669621229171753},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.5060696005821228},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.47851788997650146},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4737858474254608},{"id":"https://openalex.org/keywords/non-volatile-random-access-memory","display_name":"Non-volatile random-access memory","score":0.46527335047721863},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.45485758781433105},{"id":"https://openalex.org/keywords/conventional-memory","display_name":"Conventional memory","score":0.44400957226753235},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.39721184968948364},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3149060606956482},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2801555395126343},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.2700542211532593},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.24372082948684692},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.23326635360717773},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.14926910400390625},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.1320800483226776},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.11151313781738281},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09559795260429382}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.8484668731689453},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.7689589262008667},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6500670909881592},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.6082121133804321},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5907526612281799},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.5669621229171753},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.5060696005821228},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.47851788997650146},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4737858474254608},{"id":"https://openalex.org/C34172316","wikidata":"https://www.wikidata.org/wiki/Q499024","display_name":"Non-volatile random-access memory","level":5,"score":0.46527335047721863},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.45485758781433105},{"id":"https://openalex.org/C53838383","wikidata":"https://www.wikidata.org/wiki/Q541148","display_name":"Conventional memory","level":5,"score":0.44400957226753235},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.39721184968948364},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3149060606956482},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2801555395126343},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.2700542211532593},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.24372082948684692},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.23326635360717773},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.14926910400390625},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.1320800483226776},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.11151313781738281},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09559795260429382},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dtis.2014.6850647","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dtis.2014.6850647","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 9th IEEE International Conference on Design &amp; Technology of Integrated Systems in Nanoscale Era (DTIS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.6899999976158142}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":48,"referenced_works":["https://openalex.org/W1591621430","https://openalex.org/W1964092902","https://openalex.org/W1976905836","https://openalex.org/W1981141987","https://openalex.org/W1982533447","https://openalex.org/W1982767378","https://openalex.org/W1993062803","https://openalex.org/W1995363833","https://openalex.org/W2000321316","https://openalex.org/W2002406245","https://openalex.org/W2003633368","https://openalex.org/W2006798699","https://openalex.org/W2007750458","https://openalex.org/W2014161226","https://openalex.org/W2021853834","https://openalex.org/W2045171544","https://openalex.org/W2045354801","https://openalex.org/W2045904683","https://openalex.org/W2051133151","https://openalex.org/W2051783077","https://openalex.org/W2059323493","https://openalex.org/W2066271063","https://openalex.org/W2074357625","https://openalex.org/W2084379018","https://openalex.org/W2087532801","https://openalex.org/W2099665976","https://openalex.org/W2106935654","https://openalex.org/W2112181056","https://openalex.org/W2113797443","https://openalex.org/W2123863700","https://openalex.org/W2125223858","https://openalex.org/W2125514677","https://openalex.org/W2133690084","https://openalex.org/W2137436723","https://openalex.org/W2143483829","https://openalex.org/W2154830203","https://openalex.org/W2157061035","https://openalex.org/W2162651880","https://openalex.org/W2165911664","https://openalex.org/W2167784970","https://openalex.org/W2167906535","https://openalex.org/W2168972302","https://openalex.org/W2534547535","https://openalex.org/W3140396777","https://openalex.org/W4252884382","https://openalex.org/W6683952740","https://openalex.org/W6684474170","https://openalex.org/W6685295466"],"related_works":["https://openalex.org/W402537802","https://openalex.org/W2372007526","https://openalex.org/W1596873655","https://openalex.org/W2410132916","https://openalex.org/W2614022599","https://openalex.org/W1030357071","https://openalex.org/W1968537616","https://openalex.org/W2319558582","https://openalex.org/W2546565930","https://openalex.org/W2579594055"],"abstract_inverted_index":{"Today's":[0],"memory":[1,46],"technologies,":[2],"such":[3,73],"as":[4,31,74],"DRAM,":[5],"SRAM,":[6],"and":[7,34,91,105,110,113,119],"NAND":[8],"Flash,":[9],"are":[10,36,63],"facing":[11],"major":[12,94],"challenges":[13],"with":[14],"regard":[15],"to":[16,41,65],"their":[17],"continued":[18],"scaling.":[19],"For":[20],"instance,":[21],"ITRS":[22],"projects":[23],"that":[24],"DRAM":[25],"cannot":[26],"scale":[27],"easily":[28],"below":[29],"40nm":[30],"the":[32,44,67,117,120],"cost":[33],"energy/power":[35],"hard":[37],"-if":[38],"not":[39],"impossible-":[40],"scale.":[42],"Fortunately,":[43],"international":[45],"technology":[47,104],"community":[48],"has":[49],"been":[50],"researching":[51],"other":[52],"alternative":[53],"for":[54,70],"more":[55],"than":[56],"fifteen":[57],"years.":[58],"Apparently,":[59],"non-volatile":[60],"resistive":[61,97],"memories":[62,69],"promising":[64],"replace":[66],"today's":[68],"many":[71],"reasons":[72],"better":[75,85],"scalability,":[76],"low":[77],"cost,":[78],"higher":[79],"capacity,":[80],"lower":[81],"energy,":[82],"CMOS":[83],"compatibility,":[84],"configurability,":[86],"etc.":[87],"This":[88],"paper":[89],"discusses":[90],"highlights":[92],"three":[93],"aspects":[95],"of":[96],"memories,":[98],"especially":[99],"memristor":[100],"based":[101],"memories:":[102],"(a)":[103],"design":[106],"constraints,":[107],"(b)":[108],"architectures,":[109],"(c)":[111],"testing":[112],"design-for-test.":[114],"It":[115],"shows":[116],"opportunities":[118],"challenges.":[121]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":5},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":9},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":6},{"year":2015,"cited_by_count":9},{"year":2014,"cited_by_count":2}],"updated_date":"2026-04-21T08:09:41.155169","created_date":"2025-10-10T00:00:00"}
