{"id":"https://openalex.org/W2129161862","doi":"https://doi.org/10.1109/dsn.2010.5544920","title":"Bit-slice logic interleaving for spatial multi-bit soft-error tolerance","display_name":"Bit-slice logic interleaving for spatial multi-bit soft-error tolerance","publication_year":2010,"publication_date":"2010-06-01","ids":{"openalex":"https://openalex.org/W2129161862","doi":"https://doi.org/10.1109/dsn.2010.5544920","mag":"2129161862"},"language":"en","primary_location":{"id":"doi:10.1109/dsn.2010.5544920","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsn.2010.5544920","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE/IFIP International Conference on Dependable Systems & Networks (DSN)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049966217","display_name":"Nishant George","orcid":null},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nishant J. George","raw_affiliation_strings":["Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA","Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, 351 McCormick Rd., Charlottesville, 22904, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA","institution_ids":["https://openalex.org/I51556381"]},{"raw_affiliation_string":"Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, 351 McCormick Rd., Charlottesville, 22904, USA","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013018807","display_name":"Carl Elks","orcid":"https://orcid.org/0000-0001-5315-2698"},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Carl R. Elks","raw_affiliation_strings":["Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA","Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, 351 McCormick Rd., Charlottesville, 22904, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA","institution_ids":["https://openalex.org/I51556381"]},{"raw_affiliation_string":"Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, 351 McCormick Rd., Charlottesville, 22904, USA","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047081697","display_name":"B.W. Johnson","orcid":"https://orcid.org/0000-0003-2849-2126"},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Barry W. Johnson","raw_affiliation_strings":["Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA","Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, 351 McCormick Rd., Charlottesville, 22904, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA","institution_ids":["https://openalex.org/I51556381"]},{"raw_affiliation_string":"Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, 351 McCormick Rd., Charlottesville, 22904, USA","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5079544668","display_name":"John Lach","orcid":"https://orcid.org/0000-0002-7105-9996"},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"John Lach","raw_affiliation_strings":["Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA","Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, 351 McCormick Rd., Charlottesville, 22904, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA","institution_ids":["https://openalex.org/I51556381"]},{"raw_affiliation_string":"Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, 351 McCormick Rd., Charlottesville, 22904, USA","institution_ids":["https://openalex.org/I51556381"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I51556381"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"206","issue":null,"first_page":"141","last_page":"150"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9962999820709229,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7505616545677185},{"id":"https://openalex.org/keywords/interleaving","display_name":"Interleaving","score":0.6970517635345459},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5418042540550232},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.5269970297813416},{"id":"https://openalex.org/keywords/soft-error","display_name":"Soft error","score":0.5212210416793823},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.5004568099975586},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4950677454471588},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.48258650302886963},{"id":"https://openalex.org/keywords/logic-simulation","display_name":"Logic simulation","score":0.46416953206062317},{"id":"https://openalex.org/keywords/bit","display_name":"Bit (key)","score":0.44643720984458923},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44353851675987244},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.4434267282485962},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3577243983745575},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.23183801770210266},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15176427364349365},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.11383640766143799},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09905782341957092},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.09204700589179993}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7505616545677185},{"id":"https://openalex.org/C28034677","wikidata":"https://www.wikidata.org/wiki/Q17092530","display_name":"Interleaving","level":2,"score":0.6970517635345459},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5418042540550232},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.5269970297813416},{"id":"https://openalex.org/C154474529","wikidata":"https://www.wikidata.org/wiki/Q1658917","display_name":"Soft error","level":2,"score":0.5212210416793823},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.5004568099975586},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4950677454471588},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.48258650302886963},{"id":"https://openalex.org/C64859876","wikidata":"https://www.wikidata.org/wiki/Q173673","display_name":"Logic simulation","level":3,"score":0.46416953206062317},{"id":"https://openalex.org/C117011727","wikidata":"https://www.wikidata.org/wiki/Q1278488","display_name":"Bit (key)","level":2,"score":0.44643720984458923},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44353851675987244},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.4434267282485962},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3577243983745575},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.23183801770210266},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15176427364349365},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.11383640766143799},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09905782341957092},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.09204700589179993},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dsn.2010.5544920","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsn.2010.5544920","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE/IFIP International Conference on Dependable Systems & Networks (DSN)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320313559","display_name":"CERN","ror":"https://ror.org/01ggx4157"},{"id":"https://openalex.org/F4320337392","display_name":"Division of Electrical, Communications and Cyber Systems","ror":"https://ror.org/01krpsy48"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W160422864","https://openalex.org/W1523087909","https://openalex.org/W1935014183","https://openalex.org/W2033346530","https://openalex.org/W2034593585","https://openalex.org/W2057975896","https://openalex.org/W2074673023","https://openalex.org/W2083664225","https://openalex.org/W2100250713","https://openalex.org/W2102421762","https://openalex.org/W2107917436","https://openalex.org/W2110872719","https://openalex.org/W2116059696","https://openalex.org/W2124438715","https://openalex.org/W2126604171","https://openalex.org/W2129750565","https://openalex.org/W2131483653","https://openalex.org/W2141068710","https://openalex.org/W2152652532","https://openalex.org/W2157447136","https://openalex.org/W2167135469","https://openalex.org/W2167435539","https://openalex.org/W2168543008","https://openalex.org/W2169213530","https://openalex.org/W2312852230","https://openalex.org/W2546044294","https://openalex.org/W4231535434","https://openalex.org/W4234572373","https://openalex.org/W6606583247","https://openalex.org/W6684475336","https://openalex.org/W7036844325"],"related_works":["https://openalex.org/W2082591327","https://openalex.org/W2118487491","https://openalex.org/W2171566066","https://openalex.org/W2108396794","https://openalex.org/W2077986289","https://openalex.org/W4251160711","https://openalex.org/W4231839681","https://openalex.org/W1491122910","https://openalex.org/W2032786864","https://openalex.org/W1852211506"],"abstract_inverted_index":{"Semiconductor":[0],"devices":[1],"are":[2,18],"becoming":[3,55],"more":[4],"susceptible":[5],"to":[6,32,79,93,104],"single":[7],"event":[8],"upsets":[9],"(SEUs)":[10],"as":[11,47,101],"device":[12],"dimensions,":[13],"operating":[14],"voltages":[15],"and":[16,25,70,97],"frequencies":[17],"scaled.":[19],"The":[20],"majority":[21],"of":[22,50,74,88,115,122],"architecture-,":[23],"logic-":[24],"circuit-level":[26],"techniques":[27,78,117],"that":[28],"have":[29],"been":[30],"developed":[31],"address":[33],"SEUs":[34],"in":[35,57,91,109],"logic":[36,94],"assume":[37],"a":[38,113,119,123,127],"single-point":[39],"fault":[40,68,76],"model.":[41],"This":[42],"will":[43],"soon":[44],"be":[45],"insufficient":[46],"the":[48,72,86],"occurrence":[49],"spatial":[51,105],"multi-bit":[52,106],"errors":[53],"is":[54],"prevalent":[56],"highly":[58],"scaled":[59],"devices.":[60],"In":[61],"this":[62,66],"paper,":[63],"we":[64],"explore":[65,98],"new":[67],"model":[69],"evaluate":[71],"effectiveness":[73],"conventional":[75],"tolerance":[77],"mitigate":[80],"such":[81],"faults.":[82],"We":[83,111],"also":[84],"extend":[85],"idea":[87],"bit":[89,95],"interleaving":[90],"memory":[92],"slices":[96],"its":[99],"utility":[100],"an":[102],"approach":[103],"error":[107],"mitigation":[108],"logic.":[110],"present":[112],"comparison":[114],"these":[116],"using":[118],"case":[120],"study":[121],"Brent-Kung":[124],"adder":[125],"at":[126],"90-nm":[128],"process.":[129]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}