{"id":"https://openalex.org/W3147816099","doi":"https://doi.org/10.1109/dsd.2007.4341529","title":"Hybrid BIST Optimization Using Reseeding and Test Set Compaction","display_name":"Hybrid BIST Optimization Using Reseeding and Test Set Compaction","publication_year":2007,"publication_date":"2007-08-01","ids":{"openalex":"https://openalex.org/W3147816099","doi":"https://doi.org/10.1109/dsd.2007.4341529","mag":"3147816099"},"language":"en","primary_location":{"id":"doi:10.1109/dsd.2007.4341529","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2007.4341529","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5034460368","display_name":"Gert Jervan","orcid":"https://orcid.org/0000-0003-2237-0187"},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":true,"raw_author_name":"Gert Jervan","raw_affiliation_strings":["Department of Computer Engineering, Tallinn University of Technology, Tallinn, Estonia"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Tallinn University of Technology, Tallinn, Estonia","institution_ids":["https://openalex.org/I111112146"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052820399","display_name":"E. Orasson","orcid":null},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":false,"raw_author_name":"Elmet Orasson","raw_affiliation_strings":["Department of Computer Engineering, Tallinn University of Technology, Tallinn, Estonia"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Tallinn University of Technology, Tallinn, Estonia","institution_ids":["https://openalex.org/I111112146"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056687934","display_name":"Helena Kruus","orcid":null},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":false,"raw_author_name":"Helena Kruus","raw_affiliation_strings":["Department of Computer Engineering, Tallinn University of Technology, Tallinn, Estonia"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Tallinn University of Technology, Tallinn, Estonia","institution_ids":["https://openalex.org/I111112146"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010536057","display_name":"Raimund Ubar","orcid":"https://orcid.org/0000-0001-8186-4385"},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":false,"raw_author_name":"Raimund Ubar","raw_affiliation_strings":["Department of Computer Engineering, Tallinn University of Technology, Tallinn, Estonia"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Tallinn University of Technology, Tallinn, Estonia","institution_ids":["https://openalex.org/I111112146"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5034460368"],"corresponding_institution_ids":["https://openalex.org/I111112146"],"apc_list":null,"apc_paid":null,"fwci":0.3167,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.68177751,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"596","last_page":"603"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9939000010490417,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.819778323173523},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.7535605430603027},{"id":"https://openalex.org/keywords/pseudorandom-number-generator","display_name":"Pseudorandom number generator","score":0.7223604321479797},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.6461676359176636},{"id":"https://openalex.org/keywords/test-set","display_name":"Test set","score":0.6255475282669067},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.6103475093841553},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6073295474052429},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4925263822078705},{"id":"https://openalex.org/keywords/linear-feedback-shift-register","display_name":"Linear feedback shift register","score":0.4411613345146179},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.38032102584838867},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37232911586761475},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.34495335817337036},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20270448923110962},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.12126895785331726},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.08452385663986206},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.06488361954689026}],"concepts":[{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.819778323173523},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.7535605430603027},{"id":"https://openalex.org/C140642157","wikidata":"https://www.wikidata.org/wiki/Q1623338","display_name":"Pseudorandom number generator","level":2,"score":0.7223604321479797},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.6461676359176636},{"id":"https://openalex.org/C169903167","wikidata":"https://www.wikidata.org/wiki/Q3985153","display_name":"Test set","level":2,"score":0.6255475282669067},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.6103475093841553},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6073295474052429},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4925263822078705},{"id":"https://openalex.org/C159862308","wikidata":"https://www.wikidata.org/wiki/Q681101","display_name":"Linear feedback shift register","level":4,"score":0.4411613345146179},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.38032102584838867},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37232911586761475},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.34495335817337036},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20270448923110962},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.12126895785331726},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.08452385663986206},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.06488361954689026},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dsd.2007.4341529","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2007.4341529","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1503570386","https://openalex.org/W2022078312","https://openalex.org/W2097162292","https://openalex.org/W2104918553","https://openalex.org/W2115542812","https://openalex.org/W2144033909","https://openalex.org/W2151094122","https://openalex.org/W2152520168","https://openalex.org/W2156368823","https://openalex.org/W2171695647","https://openalex.org/W2171834616","https://openalex.org/W2536854812","https://openalex.org/W4297159816","https://openalex.org/W6681008240","https://openalex.org/W6728875092","https://openalex.org/W6843276737"],"related_works":["https://openalex.org/W1600807921","https://openalex.org/W2101477403","https://openalex.org/W2119351822","https://openalex.org/W4288754393","https://openalex.org/W2104563825","https://openalex.org/W4321517976","https://openalex.org/W2761125259","https://openalex.org/W2184933991","https://openalex.org/W1996917705","https://openalex.org/W2152745368"],"abstract_inverted_index":{"Classical":[0],"built-in":[1],"self-test":[2],"(BIST)":[3],"approaches":[4],"are":[5,30,47],"largely":[6],"based":[7,74],"on":[8,32,75],"pseudorandom":[9,44],"testing,":[10],"and":[11,22,59,77,110],"using":[12],"linear":[13],"feedback":[14],"shift":[15],"registers":[16],"(LFSR)":[17],"for":[18,70,114],"test":[19,23,45,52,62,78,87,91,96],"set":[20,79],"generation":[21],"response":[24],"compaction.":[25,80],"In":[26],"this":[27],"paper":[28],"we":[29],"concentrating":[31],"one":[33],"possible":[34],"extension":[35],"of":[36],"the":[37,56,86,101],"classical":[38],"BIST,":[39,42],"namely":[40],"hybrid":[41,71,105],"where":[43],"patterns":[46,53],"complemented":[48],"with":[49,104],"precomputed":[50],"deterministic":[51],"to":[54,60,84],"increase":[55],"fault":[57],"coverage":[58],"reduce":[61],"time.":[63],"We":[64,98],"will":[65,99],"propose":[66],"a":[67],"novel":[68],"method":[69,103],"BIST":[72,106],"optimization,":[73],"reseeding":[76],"The":[81],"objective":[82],"is":[83],"minimize":[85],"time":[88],"at":[89],"given":[90],"memory":[92],"constraints,":[93],"without":[94],"losing":[95],"quality.":[97],"compare":[100],"proposed":[102],"methods":[107],"developed":[108],"earlier":[109],"analyze":[111],"its":[112],"suitability":[113],"testing":[115],"core-based":[116],"systems.":[117]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}