{"id":"https://openalex.org/W3147061323","doi":"https://doi.org/10.1109/dsd.2007.4341484","title":"Timing- / Power-Optimization for Digital Logic Based on Standard Cells","display_name":"Timing- / Power-Optimization for Digital Logic Based on Standard Cells","publication_year":2007,"publication_date":"2007-08-01","ids":{"openalex":"https://openalex.org/W3147061323","doi":"https://doi.org/10.1109/dsd.2007.4341484","mag":"3147061323"},"language":"en","primary_location":{"id":"doi:10.1109/dsd.2007.4341484","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2007.4341484","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109343429","display_name":"H.T. Vierhaus","orcid":null},"institutions":[{"id":"https://openalex.org/I51783024","display_name":"Brandenburg University of Technology Cottbus-Senftenberg","ror":"https://ror.org/02wxx3e24","country_code":"DE","type":"education","lineage":["https://openalex.org/I51783024"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"H. T. Vierhaus","raw_affiliation_strings":["Brandenburg University of Technology, Cottbus, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Brandenburg University of Technology, Cottbus, Germany","institution_ids":["https://openalex.org/I51783024"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037417255","display_name":"H. Rossmann","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"H. Rossmann","raw_affiliation_strings":["Catena Software GmbH, Frankfurt, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Catena Software GmbH, Frankfurt, Germany","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077019877","display_name":"S. Misera","orcid":null},"institutions":[{"id":"https://openalex.org/I51783024","display_name":"Brandenburg University of Technology Cottbus-Senftenberg","ror":"https://ror.org/02wxx3e24","country_code":"DE","type":"education","lineage":["https://openalex.org/I51783024"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"S. Misera","raw_affiliation_strings":["Brandenburg University of Technology, Cottbus, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Brandenburg University of Technology, Cottbus, Germany","institution_ids":["https://openalex.org/I51783024"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.42443355,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"303","last_page":"306"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.7602578401565552},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.6834801435470581},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.6823899745941162},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.645756721496582},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5842366218566895},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5592063665390015},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.5428412556648254},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5347408652305603},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5337634682655334},{"id":"https://openalex.org/keywords/power-flow","display_name":"Power flow","score":0.4918222427368164},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4808369576931},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.4737694561481476},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.4560021162033081},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.44848525524139404},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.44741290807724},{"id":"https://openalex.org/keywords/flow","display_name":"Flow (mathematics)","score":0.43596696853637695},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2904965281486511},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.2724701166152954},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2164875566959381},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.19315141439437866},{"id":"https://openalex.org/keywords/electric-power-system","display_name":"Electric power system","score":0.18521511554718018},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.16948345303535461},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.13765352964401245}],"concepts":[{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.7602578401565552},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.6834801435470581},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.6823899745941162},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.645756721496582},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5842366218566895},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5592063665390015},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.5428412556648254},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5347408652305603},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5337634682655334},{"id":"https://openalex.org/C2986056383","wikidata":"https://www.wikidata.org/wiki/Q556030","display_name":"Power flow","level":4,"score":0.4918222427368164},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4808369576931},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.4737694561481476},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.4560021162033081},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.44848525524139404},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.44741290807724},{"id":"https://openalex.org/C38349280","wikidata":"https://www.wikidata.org/wiki/Q1434290","display_name":"Flow (mathematics)","level":2,"score":0.43596696853637695},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2904965281486511},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2724701166152954},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2164875566959381},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.19315141439437866},{"id":"https://openalex.org/C89227174","wikidata":"https://www.wikidata.org/wiki/Q2388981","display_name":"Electric power system","level":3,"score":0.18521511554718018},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.16948345303535461},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.13765352964401245},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dsd.2007.4341484","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2007.4341484","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6700000166893005,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1572101818","https://openalex.org/W1980746862","https://openalex.org/W1984588379","https://openalex.org/W2036887642","https://openalex.org/W2049804413","https://openalex.org/W2097037835","https://openalex.org/W2100912978","https://openalex.org/W2106950603","https://openalex.org/W2108368155","https://openalex.org/W2123692429","https://openalex.org/W2128054043","https://openalex.org/W2163626738"],"related_works":["https://openalex.org/W2026822479","https://openalex.org/W2345938231","https://openalex.org/W4247095439","https://openalex.org/W2146286671","https://openalex.org/W2976181145","https://openalex.org/W2102547348","https://openalex.org/W2365114398","https://openalex.org/W2337636225","https://openalex.org/W2146757344","https://openalex.org/W1975226036"],"abstract_inverted_index":{"Physical":[0],"design":[1,37,56,71,83],"for":[2,58],"digital":[3],"ICs,":[4],"based":[5],"on":[6,25,33],"standard":[7],"cells,":[8],"has":[9],"long":[10],"been":[11],"performed":[12],"without":[13,66],"explicit":[14],"consideration":[15],"of":[16,49,80],"timing":[17,52],"and":[18,28,51,60,75],"power":[19,50],"related":[20],"to":[21],"interconnects.":[22],"With":[23],"delays":[24,32],"wires":[26],"more":[27,29],"dominating":[30],"the":[31,55,70,78],"logic":[34],"paths,":[35],"such":[36,81],"styles":[38],"are":[39,85],"becoming":[40],"obsolete.":[41],"What":[42],"is":[43,45],"needed":[44],"an":[46],"iterative":[47],"inclusion":[48],"aspects":[53],"into":[54],"flow":[57,84],"placement":[59],"routing,":[61],"which":[62],"yields":[63],"economic":[64],"results":[65],"multiple":[67],"loops":[68],"in":[69,77],"flow.":[72],"Basic":[73],"problems":[74],"solutions":[76],"implementation":[79],"a":[82],"presented.":[86]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}