{"id":"https://openalex.org/W3140474894","doi":"https://doi.org/10.1109/dsd.2007.4341480","title":"Toggle Equivalence Preserving (TEP) Logic Optimization","display_name":"Toggle Equivalence Preserving (TEP) Logic Optimization","publication_year":2007,"publication_date":"2007-08-01","ids":{"openalex":"https://openalex.org/W3140474894","doi":"https://doi.org/10.1109/dsd.2007.4341480","mag":"3140474894"},"language":"en","primary_location":{"id":"doi:10.1109/dsd.2007.4341480","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2007.4341480","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110262961","display_name":"Eugene Goldberg","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Eugene Goldberg","raw_affiliation_strings":["Cadence Design Systems, USA"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012099201","display_name":"Kanupriya Gulati","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Kanupriya Gulati","raw_affiliation_strings":["Texas A and M University, USA"],"affiliations":[{"raw_affiliation_string":"Texas A and M University, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021685706","display_name":"Sunil P. Khatri","orcid":"https://orcid.org/0000-0001-7134-9929"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Sunil Khatri","raw_affiliation_strings":["Texas A and M University, USA"],"affiliations":[{"raw_affiliation_string":"Texas A and M University, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5110262961"],"corresponding_institution_ids":["https://openalex.org/I66217453"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.3620697,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"271","last_page":"279"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/equivalence","display_name":"Equivalence (formal languages)","score":0.801950216293335},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.524114727973938},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4844217598438263},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4386623799800873},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.38351547718048096},{"id":"https://openalex.org/keywords/discrete-mathematics","display_name":"Discrete mathematics","score":0.3332476317882538},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1458023190498352},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11522305011749268}],"concepts":[{"id":"https://openalex.org/C2780069185","wikidata":"https://www.wikidata.org/wiki/Q7977945","display_name":"Equivalence (formal languages)","level":2,"score":0.801950216293335},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.524114727973938},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4844217598438263},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4386623799800873},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.38351547718048096},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.3332476317882538},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1458023190498352},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11522305011749268}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/dsd.2007.4341480","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2007.4341480","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.124.6314","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.124.6314","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://eigold.tripod.com/papers/iwls-2007-tep.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W169157382","https://openalex.org/W1511688816","https://openalex.org/W2080267935","https://openalex.org/W2159658760","https://openalex.org/W3178812393","https://openalex.org/W4243754499","https://openalex.org/W6630623413"],"related_works":["https://openalex.org/W1979597421","https://openalex.org/W2007980826","https://openalex.org/W4245490552","https://openalex.org/W2061531152","https://openalex.org/W3002753104","https://openalex.org/W2077600819","https://openalex.org/W2042127053","https://openalex.org/W2142036596","https://openalex.org/W2072657027","https://openalex.org/W2600246793"],"abstract_inverted_index":{"We":[0,127],"describe":[1],"a":[2,10,62,74],"procedure":[3,27,49,60,137,146,157],"(called":[4],"the":[5,32,47,58,124,135,144,152,155],"TEP":[6,26,48,59,125,136,145,156],"procedure)":[7],"that,":[8],"given":[9],"multi-output":[11,16],"circuit":[12,17,75,90],"M,":[13],"builds":[14,87],"another":[15],"M*":[18],"that":[19],"is":[20,121],"toggle":[21,42,101],"equivalent":[22,102],"to":[23],"M.":[24],"The":[25,109],"can":[28,50],"be":[29,51],"used":[30,52],"in":[31,53,147],"following":[33],"two":[34],"scenarios.":[35],"First,":[36],"since":[37],"for":[38],"single-":[39],"output":[40],"circuits":[41,133],"equivalence":[43],"means":[44],"functional":[45],"equivalence,":[46],"\"regular\"":[54],"logic":[55],"synthesis.":[56],"Second,":[57],"enables":[61],"powerful":[63],"synthesis":[64],"method":[65],"called":[66],"LS_TE":[67,86],"(Logic":[68],"Synthesis":[69],"preserving":[70],"Toggle":[71],"Equivalence).":[72],"Given":[73],"N":[76,82,95,104,112],"and":[77,138,158],"its":[78],"partitioning":[79],"into":[80],"subcircuits":[81,94],"<sub":[83,96,105,113,118],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[84,97,106,114,119],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">i</sub>":[85,98,107,115,120],"an":[88],"optimized":[89],"N*":[91,117],"by":[92,123,134],"replacing":[93],"with":[99,116],"their":[100],"counterparts":[103],".":[108],"replacement":[110],"of":[111,130,142,154],"done":[122],"procedure.":[126],"give":[128],"results":[129,141,150],"optimizing":[131],"single-output":[132],"some":[139],"preliminary":[140],"using":[143],"LS_TE.":[148,159],"These":[149],"show":[151],"promise":[153]},"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
