{"id":"https://openalex.org/W3146128269","doi":"https://doi.org/10.1109/dsd.2007.4341471","title":"RAPANUI: A case study in Rapid Prototyping for Multiprocessor System-on-Chip","display_name":"RAPANUI: A case study in Rapid Prototyping for Multiprocessor System-on-Chip","publication_year":2007,"publication_date":"2007-08-01","ids":{"openalex":"https://openalex.org/W3146128269","doi":"https://doi.org/10.1109/dsd.2007.4341471","mag":"3146128269"},"language":"en","primary_location":{"id":"doi:10.1109/dsd.2007.4341471","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2007.4341471","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038123706","display_name":"Guillermo Pay\u00e1\u2013Vay\u00e1","orcid":"https://orcid.org/0000-0003-3503-8386"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Guillermo Paya-Vaya","raw_affiliation_strings":["Leibniz Universitat Hannover, Hannover, Niedersachsen, DE"],"affiliations":[{"raw_affiliation_string":"Leibniz Universitat Hannover, Hannover, Niedersachsen, DE","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038352122","display_name":"Javier Mart\u00edn-Langerwerf","orcid":null},"institutions":[{"id":"https://openalex.org/I114112103","display_name":"Leibniz University Hannover","ror":"https://ror.org/0304hq317","country_code":"DE","type":"education","lineage":["https://openalex.org/I114112103"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Javier Martin-Langerwerf","raw_affiliation_strings":["Institute of Microelectronic Systems, Leibniz University of Hannover, Hannover, Germany"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic Systems, Leibniz University of Hannover, Hannover, Germany","institution_ids":["https://openalex.org/I114112103"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050808949","display_name":"P. Pirsch","orcid":null},"institutions":[{"id":"https://openalex.org/I114112103","display_name":"Leibniz University Hannover","ror":"https://ror.org/0304hq317","country_code":"DE","type":"education","lineage":["https://openalex.org/I114112103"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Peter Pirsch","raw_affiliation_strings":["Institute of Microelectronic Systems, Leibniz University of Hannover, Hannover, Germany"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic Systems, Leibniz University of Hannover, Hannover, Germany","institution_ids":["https://openalex.org/I114112103"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5038123706"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.33969579,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"215","last_page":"221"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7825843095779419},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.7715852856636047},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6564152836799622},{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.6090798377990723},{"id":"https://openalex.org/keywords/workstation","display_name":"Workstation","score":0.5343775749206543},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5106578469276428},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.48280251026153564},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.42451101541519165},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.4241676330566406},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.4180545508861542},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.323644757270813},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.24888771772384644}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7825843095779419},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.7715852856636047},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6564152836799622},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.6090798377990723},{"id":"https://openalex.org/C67953723","wikidata":"https://www.wikidata.org/wiki/Q192525","display_name":"Workstation","level":2,"score":0.5343775749206543},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5106578469276428},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.48280251026153564},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.42451101541519165},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.4241676330566406},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.4180545508861542},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.323644757270813},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.24888771772384644},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dsd.2007.4341471","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2007.4341471","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1557465985","https://openalex.org/W1580327099","https://openalex.org/W2104238045","https://openalex.org/W2107831132","https://openalex.org/W2117120750","https://openalex.org/W2125476537","https://openalex.org/W2127306778","https://openalex.org/W2127955902","https://openalex.org/W2151181453","https://openalex.org/W2293635728","https://openalex.org/W2327768229","https://openalex.org/W2725179571","https://openalex.org/W6676505779"],"related_works":["https://openalex.org/W2154523322","https://openalex.org/W2083200807","https://openalex.org/W1603137082","https://openalex.org/W2364195017","https://openalex.org/W2355430452","https://openalex.org/W2049983405","https://openalex.org/W2392315374","https://openalex.org/W2114044010","https://openalex.org/W3217417506","https://openalex.org/W78498482"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"a":[3,7,39,55,71,105,117],"case":[4,51],"study":[5,52],"in":[6],"new":[8],"rapid":[9],"prototyping-based":[10],"design":[11],"framework":[12],"for":[13,20,82],"exploring":[14],"and":[15,33],"validating":[16],"complex":[17],"multiprocessor":[18,40,85],"architectures":[19],"multimedia":[21],"applications.":[22],"The":[23,50,87],"goal":[24],"of":[25,38,54,100],"the":[26,35,83,97,101,124],"presented":[27],"methodology":[28],"is":[29],"to":[30,65,70,95],"speed":[31],"up":[32,64,94],"improve":[34],"verification":[36],"flow":[37],"system":[41,60,103],"that":[42],"will":[43],"finally":[44],"be":[45,121],"implemented":[46,81],"as":[47],"an":[48],"ASIC.":[49],"consists":[53],"64-bit":[56],"compatible":[57],"AMBA":[58],"AHB":[59],"bus":[61],"which":[62],"connects":[63],"14":[66],"32-Bit":[67],"RISC":[68],"processors":[69],"host":[72],"interface.":[73],"A":[74],"typical":[75],"parallel":[76],"computing":[77],"application":[78],"has":[79],"been":[80],"parameterized":[84],"system.":[86],"employed":[88],"FPGA":[89],"emulation":[90,119],"environment":[91],"increases":[92],"by":[93],"200":[96],"simulation":[98],"frequency":[99,127],"global":[102],"on":[104],"workstation":[106],"(2.2":[107],"GHz":[108],"AMD":[109],"Dual":[110],"Opteron":[111],"with":[112],"8":[113],"GB":[114],"RAM).":[115],"Moreover":[116],"standalone":[118],"can":[120],"performed":[122],"at":[123],"maximum":[125],"achievable":[126],"(65":[128],"MHz).":[129]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
