{"id":"https://openalex.org/W3140446452","doi":"https://doi.org/10.1109/dsd.2007.4341464","title":"Functional Test-Case Generation by a Control Transaction Graph for TLM Verification","display_name":"Functional Test-Case Generation by a Control Transaction Graph for TLM Verification","publication_year":2007,"publication_date":"2007-08-01","ids":{"openalex":"https://openalex.org/W3140446452","doi":"https://doi.org/10.1109/dsd.2007.4341464","mag":"3140446452"},"language":"en","primary_location":{"id":"doi:10.1109/dsd.2007.4341464","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2007.4341464","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054928425","display_name":"Mohammad Reza Kakoee","orcid":null},"institutions":[{"id":"https://openalex.org/I110525433","display_name":"Islamic Azad University, Tehran","ror":"https://ror.org/01kzn7k21","country_code":"IR","type":"education","lineage":["https://openalex.org/I110525433"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Mohammad Reza Kakoee","raw_affiliation_strings":["Computer Engineering, Islamic Azad University\uc2a0, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering, Islamic Azad University\uc2a0, Tehran, Iran","institution_ids":["https://openalex.org/I110525433"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029842847","display_name":"M.H. Neishaburi","orcid":null},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"M.H Neishaburi","raw_affiliation_strings":["Electrical and Computer Engineering, University of Tehran, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, University of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5053012913","display_name":"Siamak Mohammadi","orcid":"https://orcid.org/0000-0003-1515-7281"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Siamak Mohammadi","raw_affiliation_strings":["Electrical and Computer Engineering, University of Tehran, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, University of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3184,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.68585636,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"157","last_page":"164"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7929689884185791},{"id":"https://openalex.org/keywords/database-transaction","display_name":"Database transaction","score":0.6059388518333435},{"id":"https://openalex.org/keywords/control-flow-graph","display_name":"Control flow graph","score":0.5934953689575195},{"id":"https://openalex.org/keywords/control-flow","display_name":"Control flow","score":0.5449331402778625},{"id":"https://openalex.org/keywords/test-case","display_name":"Test case","score":0.5137349367141724},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.5134573578834534},{"id":"https://openalex.org/keywords/code-coverage","display_name":"Code coverage","score":0.5046757459640503},{"id":"https://openalex.org/keywords/transaction-level-modeling","display_name":"Transaction-level modeling","score":0.4839463531970978},{"id":"https://openalex.org/keywords/model-checking","display_name":"Model checking","score":0.47925496101379395},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.4492201507091522},{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.4477713108062744},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.43859875202178955},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.33745190501213074},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3076587915420532},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.16655728220939636}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7929689884185791},{"id":"https://openalex.org/C75949130","wikidata":"https://www.wikidata.org/wiki/Q848010","display_name":"Database transaction","level":2,"score":0.6059388518333435},{"id":"https://openalex.org/C27458966","wikidata":"https://www.wikidata.org/wiki/Q1187693","display_name":"Control flow graph","level":2,"score":0.5934953689575195},{"id":"https://openalex.org/C160191386","wikidata":"https://www.wikidata.org/wiki/Q868299","display_name":"Control flow","level":2,"score":0.5449331402778625},{"id":"https://openalex.org/C128942645","wikidata":"https://www.wikidata.org/wiki/Q1568346","display_name":"Test case","level":3,"score":0.5137349367141724},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.5134573578834534},{"id":"https://openalex.org/C53942775","wikidata":"https://www.wikidata.org/wiki/Q1211721","display_name":"Code coverage","level":3,"score":0.5046757459640503},{"id":"https://openalex.org/C169571997","wikidata":"https://www.wikidata.org/wiki/Q966099","display_name":"Transaction-level modeling","level":3,"score":0.4839463531970978},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.47925496101379395},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.4492201507091522},{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.4477713108062744},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.43859875202178955},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.33745190501213074},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3076587915420532},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.16655728220939636},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C152877465","wikidata":"https://www.wikidata.org/wiki/Q208042","display_name":"Regression analysis","level":2,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dsd.2007.4341464","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2007.4341464","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W154106227","https://openalex.org/W192912203","https://openalex.org/W1583548393","https://openalex.org/W2043292640","https://openalex.org/W2107629078","https://openalex.org/W2143062031","https://openalex.org/W2159419471","https://openalex.org/W2481725867","https://openalex.org/W4238435901","https://openalex.org/W4247397443","https://openalex.org/W4255608508","https://openalex.org/W6607880141","https://openalex.org/W6661076086","https://openalex.org/W6820139873"],"related_works":["https://openalex.org/W2533881872","https://openalex.org/W2301151507","https://openalex.org/W1596567466","https://openalex.org/W2183605704","https://openalex.org/W2585026057","https://openalex.org/W2073197595","https://openalex.org/W1525398417","https://openalex.org/W2358909550","https://openalex.org/W1975665243","https://openalex.org/W2069603759"],"abstract_inverted_index":{"Transaction":[0],"level":[1,63,131],"modeling":[2],"allows":[3],"exploring":[4],"several":[5],"SoC":[6],"design":[7,105],"architectures":[8],"leading":[9],"to":[10,38,72,158],"better":[11],"performance":[12],"and":[13,106,143,182],"easier":[14],"verification":[15,46],"of":[16,30,47,53,64,88,100,162,175,189],"the":[17,28,45,51,86,104,109,115,124,160,163,172,187],"final":[18],"product.":[19],"Test":[20],"cases":[21,58],"play":[22],"an":[23],"important":[24],"role":[25],"in":[26,70,103,141],"determining":[27],"quality":[29,161],"a":[31,48,76,81,89,96,101,129,155,179],"design.":[32],"Inadequate":[33],"test-cases":[34,74,127],"may":[35],"cause":[36],"bugs":[37],"remain":[39],"after":[40],"verification.":[41],"Although":[42],"TLM":[43],"expedites":[44],"hardware":[49],"design,":[50],"problem":[52],"having":[54],"high":[55],"coverage":[56,152],"test":[57],"remains":[59],"unsettled":[60],"at":[61],"this":[62,67,190],"abstraction.":[65],"In":[66],"paper,":[68],"first,":[69],"order":[71],"generate":[73,183],"for":[75,128,154],"TL":[77,90,156],"model":[78,157,174],"we":[79,118,167],"present":[80],"Control-Transaction":[82],"Graph":[83,94],"(CTG)":[84],"describing":[85],"behavior":[87],"Model.":[91],"A":[92],"Control":[93],"is":[95],"control":[97],"flow":[98],"graph":[99],"module":[102],"Transactions":[107],"represent":[108],"interactions":[110],"such":[111],"as":[112,126,178],"synchronization":[113],"between":[114],"modules.":[116],"Second,":[117],"define":[119],"dependent":[120],"paths":[121],"(DePaths)":[122],"on":[123,171,186],"CTG":[125,188],"transaction":[130],"model.":[132,191],"The":[133],"generated":[134,164],"DePaths":[135],"can":[136],"find":[137],"some":[138],"communication":[139],"errors":[140],"simulation":[142],"detect":[144],"unreachable":[145],"statements":[146],"concerning":[147],"interactions.":[148],"We":[149],"also":[150],"give":[151],"metrics":[153],"measure":[159],"test-cases.":[165],"Finally,":[166],"apply":[168],"our":[169],"method":[170],"SystemC":[173],"AMBA-AHB":[176],"bus":[177],"case":[180],"study":[181],"testcases":[184],"based":[185]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
