{"id":"https://openalex.org/W3149303973","doi":"https://doi.org/10.1109/dsd.2007.4341461","title":"Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays","display_name":"Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays","publication_year":2007,"publication_date":"2007-08-01","ids":{"openalex":"https://openalex.org/W3149303973","doi":"https://doi.org/10.1109/dsd.2007.4341461","mag":"3149303973"},"language":"en","primary_location":{"id":"doi:10.1109/dsd.2007.4341461","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2007.4341461","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024859835","display_name":"Scott W. Miller","orcid":null},"institutions":[{"id":"https://openalex.org/I212119943","display_name":"University of Victoria","ror":"https://ror.org/04s5mat29","country_code":"CA","type":"education","lineage":["https://openalex.org/I212119943"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Scott MILLER","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Victoria, Victoria, BC, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Victoria, Victoria, BC, Canada","institution_ids":["https://openalex.org/I212119943"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057365306","display_name":"Mihai Sima","orcid":"https://orcid.org/0000-0002-1945-5190"},"institutions":[{"id":"https://openalex.org/I212119943","display_name":"University of Victoria","ror":"https://ror.org/04s5mat29","country_code":"CA","type":"education","lineage":["https://openalex.org/I212119943"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Mihai SIMA","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Victoria, Victoria, BC, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Victoria, Victoria, BC, Canada","institution_ids":["https://openalex.org/I212119943"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072436975","display_name":"Michael McGuire","orcid":"https://orcid.org/0000-0001-7343-959X"},"institutions":[{"id":"https://openalex.org/I212119943","display_name":"University of Victoria","ror":"https://ror.org/04s5mat29","country_code":"CA","type":"education","lineage":["https://openalex.org/I212119943"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Michael McGUIRE","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Victoria, Victoria, BC, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Victoria, Victoria, BC, Canada","institution_ids":["https://openalex.org/I212119943"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5024859835"],"corresponding_institution_ids":["https://openalex.org/I212119943"],"apc_list":null,"apc_paid":null,"fwci":0.7025,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.76590808,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"21","issue":null,"first_page":"138","last_page":"146"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.9556444883346558},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.6356017589569092},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5185609459877014},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5180302262306213},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.49920201301574707},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.49493616819381714},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.436110258102417},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.42088618874549866},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3667421340942383},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2613959312438965}],"concepts":[{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.9556444883346558},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.6356017589569092},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5185609459877014},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5180302262306213},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.49920201301574707},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.49493616819381714},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.436110258102417},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.42088618874549866},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3667421340942383},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2613959312438965}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dsd.2007.4341461","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2007.4341461","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.9100000262260437,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320310709","display_name":"CMC Microsystems","ror":"https://ror.org/03k70ea39"},{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W1481987700","https://openalex.org/W1491885026","https://openalex.org/W1502531259","https://openalex.org/W1522950391","https://openalex.org/W1523051745","https://openalex.org/W1527137186","https://openalex.org/W1535610321","https://openalex.org/W1604323946","https://openalex.org/W1830708738","https://openalex.org/W2000260960","https://openalex.org/W2001824086","https://openalex.org/W2007049691","https://openalex.org/W2058996914","https://openalex.org/W2061433717","https://openalex.org/W2095558812","https://openalex.org/W2109817800","https://openalex.org/W2127936519","https://openalex.org/W2138840350","https://openalex.org/W2138841914","https://openalex.org/W2151731855","https://openalex.org/W2154778518","https://openalex.org/W2155062435","https://openalex.org/W2160130898","https://openalex.org/W2167939365","https://openalex.org/W2169278276","https://openalex.org/W3103339143","https://openalex.org/W3152435103","https://openalex.org/W4238999275","https://openalex.org/W6638478215","https://openalex.org/W6676555232"],"related_works":["https://openalex.org/W4386261925","https://openalex.org/W2082944690","https://openalex.org/W2263373136","https://openalex.org/W2006330903","https://openalex.org/W2478796561","https://openalex.org/W91469557","https://openalex.org/W4245780952","https://openalex.org/W1997318576","https://openalex.org/W2135286216","https://openalex.org/W3129152221"],"abstract_inverted_index":{"Programmable":[0],"routing":[1],"and":[2,48,174,205],"logic":[3,26,136,161],"in":[4,57,166],"field-programmable":[5],"gate":[6],"arrays":[7],"are":[8],"implemented":[9],"using":[10],"nMOS":[11,21,108,172],"pass":[12],"transistors.":[13],"Since":[14],"the":[15,24,29,33,65,71,89,107,111,128,144,148,151,154,167,171,175,179,189,197],"threshold":[16],"voltage":[17],"drop":[18],"across":[19,200],"an":[20,58,62,185],"device":[22],"degrades":[23,70],"high":[25,135],"value,":[27],"causing":[28],"pMOS":[30,54,176],"transistor":[31,55],"of":[32,61,110,127,153,159,178,188,194],"downstream":[34,112,145,180],"buffer":[35,146],"to":[36,83,105],"not":[37],"turn":[38],"fully":[39],"off,":[40],"this":[41],"approach":[42,199],"suffers":[43],"from":[44,124,139],"static":[45,66],"power":[46,67,76,94],"consumption":[47,95],"reduced":[49],"noise":[50],"margins.":[51],"The":[52,157,182],"standard":[53,198],"pull-up":[56],"active":[59,75,93],"feedback":[60],"inverter":[63],"reduces":[64],"consumption,":[68],"but":[69],"switching":[72],"time":[73],"and/or":[74],"consumption.":[77],"We":[78],"propose":[79],"a":[80,97,120],"circuit":[81],"technique":[82],"build":[84],"level-restoring":[85],"buffers,":[86],"which":[87],"improves":[88],"propagation":[90],"delay":[91,149],"or":[92,150],"at":[96],"tiny":[98],"area":[99],"penalty.":[100],"Our":[101],"main":[102],"idea":[103],"is":[104,117,163],"replicate":[106],"element":[109,177],"buffer,":[113],"where":[114],"each":[115],"replica":[116],"driven":[118],"by":[119,170],"signal":[121],"that":[122],"originates":[123],"earlier":[125,140],"stages":[126,141],"nMOS-tree":[129],"multiplexer.":[130],"This":[131],"way,":[132],"when":[133],"passing":[134,158],"values,":[137],"signals":[138],"directly":[142],"drive":[143],"improving":[147],"slope":[152],"transition":[155],"edge.":[156],"low":[160],"values":[162],"still":[164],"performed":[165],"original":[168],"way":[169],"tree":[173],"buffer.":[181],"simulations":[183],"indicate":[184],"average":[186],"improvement":[187],"composite":[190],"metric":[191],"area-delay-energy":[192],"product":[193],"25%":[195],"versus":[196],"180":[201],"nm,":[202,204],"130":[203],"90":[206],"nm":[207],"technologies.":[208]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}