{"id":"https://openalex.org/W3151501953","doi":"https://doi.org/10.1109/dsd.2007.4341452","title":"An Implementation of an Address Generator Using Hash Memories","display_name":"An Implementation of an Address Generator Using Hash Memories","publication_year":2007,"publication_date":"2007-08-01","ids":{"openalex":"https://openalex.org/W3151501953","doi":"https://doi.org/10.1109/dsd.2007.4341452","mag":"3151501953"},"language":"en","primary_location":{"id":"doi:10.1109/dsd.2007.4341452","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2007.4341452","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038081233","display_name":"Tsutomu Sasao","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Tsutomu Sasao","raw_affiliation_strings":["Kyushu Kogyo Daigaku, Kitakyushu, Fukuoka, JP"],"affiliations":[{"raw_affiliation_string":"Kyushu Kogyo Daigaku, Kitakyushu, Fukuoka, JP","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101052791","display_name":"Munehiro Matsuura","orcid":null},"institutions":[{"id":"https://openalex.org/I207014233","display_name":"Kyushu Institute of Technology","ror":"https://ror.org/02278tr80","country_code":"JP","type":"education","lineage":["https://openalex.org/I207014233"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Munehiro Matsuura","raw_affiliation_strings":["Department of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka, Japan","institution_ids":["https://openalex.org/I207014233"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5038081233"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.7999,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":{"value":0.93538125,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"1800","issue":null,"first_page":"69","last_page":"76"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10714","display_name":"Software-Defined Networks and 5G","score":0.9649999737739563,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10400","display_name":"Network Security and Intrusion Detection","score":0.9635999798774719,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/generator","display_name":"Generator (circuit theory)","score":0.7709046602249146},{"id":"https://openalex.org/keywords/hash-function","display_name":"Hash function","score":0.7385051846504211},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7340953350067139},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7320337891578674},{"id":"https://openalex.org/keywords/sha-2","display_name":"SHA-2","score":0.48545485734939575},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.46063125133514404},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4050973057746887},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3762253522872925},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.363455593585968},{"id":"https://openalex.org/keywords/hash-chain","display_name":"Hash chain","score":0.3211875557899475},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2353896200656891}],"concepts":[{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.7709046602249146},{"id":"https://openalex.org/C99138194","wikidata":"https://www.wikidata.org/wiki/Q183427","display_name":"Hash function","level":2,"score":0.7385051846504211},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7340953350067139},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7320337891578674},{"id":"https://openalex.org/C190157925","wikidata":"https://www.wikidata.org/wiki/Q1968605","display_name":"SHA-2","level":4,"score":0.48545485734939575},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.46063125133514404},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4050973057746887},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3762253522872925},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.363455593585968},{"id":"https://openalex.org/C135783594","wikidata":"https://www.wikidata.org/wiki/Q5678864","display_name":"Hash chain","level":3,"score":0.3211875557899475},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2353896200656891},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dsd.2007.4341452","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2007.4341452","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320334764","display_name":"Japan Society for the Promotion of Science","ror":"https://ror.org/00hhkn466"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1481714151","https://openalex.org/W1586713396","https://openalex.org/W1597348009","https://openalex.org/W1975889363","https://openalex.org/W2041871970","https://openalex.org/W2043230098","https://openalex.org/W2062143991","https://openalex.org/W2125458961","https://openalex.org/W2142819919","https://openalex.org/W4236444653"],"related_works":["https://openalex.org/W3151879525","https://openalex.org/W2154676777","https://openalex.org/W4252190074","https://openalex.org/W2982222368","https://openalex.org/W4200497776","https://openalex.org/W2103058157","https://openalex.org/W2069568684","https://openalex.org/W2110701844","https://openalex.org/W122749164","https://openalex.org/W2509647301"],"abstract_inverted_index":{"An":[0],"address":[1,6,38],"generator":[2],"produces":[3,23],"a":[4],"unique":[5],"from":[7],"1":[8],"to":[9,16,35,71],"k":[10,19],"for":[11,25],"the":[12,31,47,51,55,59,63,78,98,101],"input":[13],"that":[14,81,97],"matches":[15],"one":[17],"of":[18,46,58,86,93,100],"registered":[20,48,60,75],"vectors,":[21,49],"and":[22],"0":[24],"other":[26],"inputs.":[27],"This":[28],"paper":[29],"presents":[30],"super":[32,64],"hybrid":[33,65],"method":[34,80],"design":[36],"an":[37,87],"generator.":[39],"The":[40],"hash":[41],"memories":[42],"realize":[43],"about":[44],"96%":[45],"while":[50],"reconfigurable":[52],"PLA":[53],"realizes":[54],"remaining":[56],"4%":[57],"vectors.":[61],"With":[62],"method,":[66],"we":[67],"can":[68],"implement":[69],"up":[70],"20":[72],"times":[73],"more":[74],"vectors":[76],"than":[77],"conventional":[79],"uses":[82],"only":[83],"logic":[84],"elements":[85],"FPGA.":[88],"Experimental":[89],"results":[90],"using":[91],"lists":[92],"English":[94],"words":[95],"show":[96],"usefulness":[99],"approach.":[102]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2014,"cited_by_count":3},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}