{"id":"https://openalex.org/W2146477632","doi":"https://doi.org/10.1109/dsd.2003.1231969","title":"Back-traced deductive-parallel fault simulation for digital systems","display_name":"Back-traced deductive-parallel fault simulation for digital systems","publication_year":2003,"publication_date":"2003-01-01","ids":{"openalex":"https://openalex.org/W2146477632","doi":"https://doi.org/10.1109/dsd.2003.1231969","mag":"2146477632"},"language":"en","primary_location":{"id":"doi:10.1109/dsd.2003.1231969","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2003.1231969","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Euromicro Symposium on Digital System Design, 2003. Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044434351","display_name":"Vladimir Hahanov","orcid":"https://orcid.org/0000-0001-5312-5841"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"V. Hahanov","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010536057","display_name":"Raimund Ubar","orcid":"https://orcid.org/0000-0001-8186-4385"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"R. Ubar","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5070139288","display_name":"S. Hyduke","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"S. Hyduke","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"4","issue":null,"first_page":"370","last_page":"377"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.994700014591217,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9642999768257141,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.7575386762619019},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7513678073883057},{"id":"https://openalex.org/keywords/superposition-principle","display_name":"Superposition principle","score":0.6103897094726562},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.5859981775283813},{"id":"https://openalex.org/keywords/deductive-database","display_name":"Deductive database","score":0.4719005525112152},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.4128859043121338},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.35707390308380127},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3540774881839752},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.2901803255081177},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12074211239814758},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.0822238028049469}],"concepts":[{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.7575386762619019},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7513678073883057},{"id":"https://openalex.org/C27753989","wikidata":"https://www.wikidata.org/wiki/Q284885","display_name":"Superposition principle","level":2,"score":0.6103897094726562},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.5859981775283813},{"id":"https://openalex.org/C2777502361","wikidata":"https://www.wikidata.org/wiki/Q1182254","display_name":"Deductive database","level":2,"score":0.4719005525112152},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.4128859043121338},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.35707390308380127},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3540774881839752},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.2901803255081177},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12074211239814758},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0822238028049469},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dsd.2003.1231969","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2003.1231969","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Euromicro Symposium on Digital System Design, 2003. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W1554885925","https://openalex.org/W1826384324"],"related_works":["https://openalex.org/W4308749380","https://openalex.org/W2037841693","https://openalex.org/W2372481764","https://openalex.org/W1977264433","https://openalex.org/W2746368218","https://openalex.org/W4308448008","https://openalex.org/W2163047760","https://openalex.org/W2955439067","https://openalex.org/W1519923721","https://openalex.org/W3147676363"],"abstract_inverted_index":{"A":[0],"high":[1],"performance":[2],"back-traced":[3],"deductive-parallel":[4],"(BDP)":[5],"fault":[6],"simulation":[7],"method":[8,48],"based":[9],"on":[10,16],"the":[11,46],"superposition":[12],"procedure":[13],"is":[14,30],"oriented":[15],"using":[17],"large":[18],"digital":[19],"designs":[20],"processing.":[21],"Evaluation":[22],"of":[23,45],"RT":[24],"and":[25,38,49],"gate":[26],"level":[27],"design":[28],"description":[29],"proposed":[31,47],"in":[32],"this":[33],"work.":[34],"The":[35],"data":[36],"structure":[37],"program":[39],"are":[40],"developed":[41],"for":[42],"algorithms":[43],"realization":[44],"integration":[50],"with":[51],"automatic":[52],"test":[53],"pattern":[54],"generation":[55],"systems.":[56]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}