{"id":"https://openalex.org/W2106965063","doi":"https://doi.org/10.1109/dsd.2003.1231917","title":"Information-driven library-based circuit synthesis","display_name":"Information-driven library-based circuit synthesis","publication_year":2003,"publication_date":"2003-01-01","ids":{"openalex":"https://openalex.org/W2106965063","doi":"https://doi.org/10.1109/dsd.2003.1231917","mag":"2106965063"},"language":"en","primary_location":{"id":"doi:10.1109/dsd.2003.1231917","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2003.1231917","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Euromicro Symposium on Digital System Design, 2003. Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109220541","display_name":"L. J\u00f3\u017awiak","orcid":null},"institutions":[{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"L. Jozwiak","raw_affiliation_strings":["Eindhovan University of Technology, Eindhoven, Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Eindhovan University of Technology, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I83019370"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005329636","display_name":"S. Biega\u0144ski","orcid":null},"institutions":[{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"S. Bieganski","raw_affiliation_strings":["Eindhovan University of Technology, Eindhoven, Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Eindhovan University of Technology, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I83019370"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065137478","display_name":"A. Chojnacki","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"A. Chojnacki","raw_affiliation_strings":["PDF Solutions, Inc.orporated, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"PDF Solutions, Inc.orporated, CA, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.2923,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.79486485,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"15","issue":null,"first_page":"148","last_page":"155"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6858625411987305},{"id":"https://openalex.org/keywords/decomposition","display_name":"Decomposition","score":0.584398090839386},{"id":"https://openalex.org/keywords/microelectronics","display_name":"Microelectronics","score":0.5822175741195679},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.5547180771827698},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.5055227279663086},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5031525492668152},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.47613075375556946},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4507765471935272},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.44902172684669495},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.44104188680648804},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3987845778465271},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3373621106147766},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.2877858281135559},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2330823838710785},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19587257504463196},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.13570243120193481},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.12299749255180359}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6858625411987305},{"id":"https://openalex.org/C124681953","wikidata":"https://www.wikidata.org/wiki/Q339062","display_name":"Decomposition","level":2,"score":0.584398090839386},{"id":"https://openalex.org/C187937830","wikidata":"https://www.wikidata.org/wiki/Q175403","display_name":"Microelectronics","level":2,"score":0.5822175741195679},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.5547180771827698},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.5055227279663086},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5031525492668152},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.47613075375556946},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4507765471935272},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.44902172684669495},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.44104188680648804},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3987845778465271},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3373621106147766},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.2877858281135559},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2330823838710785},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19587257504463196},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.13570243120193481},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.12299749255180359},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/dsd.2003.1231917","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2003.1231917","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Euromicro Symposium on Digital System Design, 2003. Proceedings.","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.tue.nl:openaire_cris_publications/7ce5b430-5d3c-4acb-98a8-17a3999723da","is_oa":false,"landing_page_url":"https://research.tue.nl/en/publications/7ce5b430-5d3c-4acb-98a8-17a3999723da","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Jozwiak, L, Bieganski, S J & Chojnacki, A 2003, Information-driven library-based circuit synthesis. in DSD'2003 Euromicro Symposium on Digital System Design. IEEE Computer Society, Los Alamitos CA, USA, pp. 148-155, 6th Euromicro Symposium on Digital Systems Design (DSD 2003), Belek, Turkey, 1/09/03. https://doi.org/10.1109/DSD.2003.1231917","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:tue:oai:pure.tue.nl:publications/7ce5b430-5d3c-4acb-98a8-17a3999723da","is_oa":false,"landing_page_url":"https://research.tue.nl/nl/publications/7ce5b430-5d3c-4acb-98a8-17a3999723da","pdf_url":null,"source":{"id":"https://openalex.org/S4306401843","display_name":"Data Archiving and Networked Services (DANS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1322597698","host_organization_name":"Royal Netherlands Academy of Arts and Sciences","host_organization_lineage":["https://openalex.org/I1322597698"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"DSD'2003 Euromicro Symposium on Digital System Design, 148 - 155","raw_type":"info:eu-repo/semantics/conferencepaper"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1511688816","https://openalex.org/W1967845326","https://openalex.org/W1974711669","https://openalex.org/W2015415966","https://openalex.org/W2041634996","https://openalex.org/W2068422506","https://openalex.org/W2086358525","https://openalex.org/W2093176534","https://openalex.org/W2096041455","https://openalex.org/W2110619112","https://openalex.org/W2117956479","https://openalex.org/W2118283917","https://openalex.org/W2126761930","https://openalex.org/W2140127333","https://openalex.org/W2140727935","https://openalex.org/W2159724425","https://openalex.org/W2160903885","https://openalex.org/W2539416049","https://openalex.org/W2807744573","https://openalex.org/W4230046868","https://openalex.org/W4231267350","https://openalex.org/W4241671559","https://openalex.org/W4255564979"],"related_works":["https://openalex.org/W2170184215","https://openalex.org/W2072840391","https://openalex.org/W818963952","https://openalex.org/W2039140951","https://openalex.org/W2390607226","https://openalex.org/W2157277696","https://openalex.org/W2018106661","https://openalex.org/W1939541994","https://openalex.org/W2393658466","https://openalex.org/W1851795671"],"abstract_inverted_index":{"The":[0,50,79],"opportunities":[1],"created":[2],"by":[3],"modern":[4],"microelectronic":[5],"technology":[6],"cannot":[7],"be":[8],"effectively":[9],"and":[10,65,101],"efficiently":[11],"exploited,":[12],"because":[13],"of":[14,16,67],"weaknesses":[15],"the":[17,46,83,90,94],"traditional":[18],"circuit":[19,33,60,85],"synthesis":[20,34,86],"methods":[21],"used":[22],"in":[23],"today's":[24],"CAD":[25],"tools.":[26],"In":[27],"this":[28],"paper,":[29],"a":[30],"new":[31],"information-driven":[32,57,95],"method":[35,51,91],"is":[36,52],"discussed":[37],"that":[38,88,93],"targets":[39],"combinational":[40],"circuits":[41],"implemented":[42],"with":[43],"gates":[44],"from":[45,74,82],"pre-characterized":[47],"gate":[48],"libraries.":[49],"based":[53],"on":[54],"our":[55],"original":[56],"approach":[58],"to":[59],"synthesis,":[61],"bottom-up":[62],"general":[63,96],"decomposition":[64,97],"theory":[66],"information":[68],"relationship":[69],"measures.":[70],"It":[71],"differs":[72],"considerably":[73],"all":[75],"other":[76],"known":[77],"methods.":[78],"experimental":[80],"results":[81],"automatic":[84],"tool":[87],"implements":[89],"demonstrate":[92],"produces":[98],"very":[99],"fast":[100],"compact":[102],"gate-based":[103],"circuits.":[104]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}