{"id":"https://openalex.org/W2116174838","doi":"https://doi.org/10.1109/dsd.2003.1231909","title":"Exploring storage organization in ASIP synthesis","display_name":"Exploring storage organization in ASIP synthesis","publication_year":2003,"publication_date":"2003-01-01","ids":{"openalex":"https://openalex.org/W2116174838","doi":"https://doi.org/10.1109/dsd.2003.1231909","mag":"2116174838"},"language":"en","primary_location":{"id":"doi:10.1109/dsd.2003.1231909","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2003.1231909","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Euromicro Symposium on Digital System Design, 2003. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063166765","display_name":"Manoj Jain","orcid":"https://orcid.org/0000-0002-3582-9527"},"institutions":[{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"M.K. Jain","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology Delhi, India","[Department of Computer Science and Engineering, Indian Institute of Technology, Delhi, India.]"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology Delhi, India","institution_ids":["https://openalex.org/I68891433"]},{"raw_affiliation_string":"[Department of Computer Science and Engineering, Indian Institute of Technology, Delhi, India.]","institution_ids":["https://openalex.org/I68891433"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102857440","display_name":"S. Balakrishnan","orcid":null},"institutions":[{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"M. Balakrishnan","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology Delhi, India","[Department of Computer Science and Engineering, Indian Institute of Technology, Delhi, India.]"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology Delhi, India","institution_ids":["https://openalex.org/I68891433"]},{"raw_affiliation_string":"[Department of Computer Science and Engineering, Indian Institute of Technology, Delhi, India.]","institution_ids":["https://openalex.org/I68891433"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101478917","display_name":"Anshul Kumar","orcid":"https://orcid.org/0000-0002-3871-5402"},"institutions":[{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"A. Kumar","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology Delhi, India","[Department of Computer Science and Engineering, Indian Institute of Technology, Delhi, India.]"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology Delhi, India","institution_ids":["https://openalex.org/I68891433"]},{"raw_affiliation_string":"[Department of Computer Science and Engineering, Indian Institute of Technology, Delhi, India.]","institution_ids":["https://openalex.org/I68891433"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5063166765"],"corresponding_institution_ids":["https://openalex.org/I68891433"],"apc_list":null,"apc_paid":null,"fwci":0.2476,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.55528531,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"120","last_page":"127"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8747396469116211},{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.7725792527198792},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7079111337661743},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5776617527008057},{"id":"https://openalex.org/keywords/context-switch","display_name":"Context switch","score":0.5087805390357971},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.5067852139472961},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.4793975353240967},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.47790464758872986},{"id":"https://openalex.org/keywords/processor-register","display_name":"Processor register","score":0.42335209250450134},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4199157953262329},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.41751962900161743},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3635147213935852},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2649078667163849},{"id":"https://openalex.org/keywords/memory-address","display_name":"Memory address","score":0.11552175879478455}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8747396469116211},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.7725792527198792},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7079111337661743},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5776617527008057},{"id":"https://openalex.org/C53833338","wikidata":"https://www.wikidata.org/wiki/Q1061424","display_name":"Context switch","level":2,"score":0.5087805390357971},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.5067852139472961},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.4793975353240967},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.47790464758872986},{"id":"https://openalex.org/C2871975","wikidata":"https://www.wikidata.org/wiki/Q187466","display_name":"Processor register","level":4,"score":0.42335209250450134},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4199157953262329},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.41751962900161743},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3635147213935852},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2649078667163849},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.11552175879478455},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/dsd.2003.1231909","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2003.1231909","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Euromicro Symposium on Digital System Design, 2003. Proceedings.","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.5.2529","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.5.2529","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cse.iitd.ernet.in/esproject/homepage/docs/pubs/manoj_dsd03.ps.gz","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.95.7905","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.95.7905","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://eprint.iitd.ac.in/dspace/bitstream/2074/2094/1/jainexp2003.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.4000000059604645,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1585371887","https://openalex.org/W1746775577","https://openalex.org/W1975323530","https://openalex.org/W2011734692","https://openalex.org/W2038788520","https://openalex.org/W2045555750","https://openalex.org/W2060490513","https://openalex.org/W2118159862","https://openalex.org/W2133287941","https://openalex.org/W2137366678","https://openalex.org/W2140369700","https://openalex.org/W2156810920","https://openalex.org/W2170990025","https://openalex.org/W2171595223","https://openalex.org/W2171690753","https://openalex.org/W4230872265","https://openalex.org/W4236145149","https://openalex.org/W4239584669","https://openalex.org/W4242934305","https://openalex.org/W4252727414","https://openalex.org/W6634861328","https://openalex.org/W6637928269","https://openalex.org/W6824577725"],"related_works":["https://openalex.org/W1967889241","https://openalex.org/W2111377238","https://openalex.org/W2161297616","https://openalex.org/W3117494601","https://openalex.org/W4247209662","https://openalex.org/W2195435904","https://openalex.org/W2148662141","https://openalex.org/W2159389028","https://openalex.org/W2224192221","https://openalex.org/W2884590322"],"abstract_inverted_index":{"Performance":[0],"estimation":[1],"which":[2,46],"drives":[3],"the":[4,17,28,94,123,162],"design":[5,18],"space":[6],"exploration":[7],"is":[8,119,137],"usually":[9],"done":[10],"by":[11,42,92,157],"simulation.":[12],"With":[13],"increasing":[14],"dimensions":[15],"of":[16,30,74,96,113,131,155],"space,":[19],"simulator":[20,136],"based":[21,44,53,66],"approaches":[22,54],"become":[23],"too":[24],"time":[25,124],"consuming.":[26],"In":[27],"domain":[29],"application":[31],"specific":[32],"instruction":[33],"set":[34],"processors":[35,156,170],"(ASIP),":[36],"this":[37],"problem":[38],"can":[39],"be":[40],"solved":[41],"scheduler":[43,52,65],"approaches,":[45],"are":[47,90],"much":[48],"faster.":[49],"However,":[50],"existing":[51],"do":[55],"not":[56,106],"help":[57],"in":[58,80],"exploring":[59,69],"storage":[60],"organization.":[61],"We":[62],"present":[63],"a":[64,128,153],"technique":[67,103,145],"for":[68,85,121,139,149],"register":[70,75,87,109,132],"file":[71,88],"size,":[72],"number":[73,95,112,130],"windows":[76,133],"and":[77,99,134,174],"cache":[78,135,141],"configurations":[79],"an":[81],"integrated":[82],"manner.":[83],"Performances":[84],"different":[86],"sizes":[89],"estimated":[91,120],"predicting":[93],"memory":[97],"spills":[98,118],"its":[100],"delay.":[101],"The":[102,111,143,169],"employed":[104],"does":[105],"require":[107],"explicit":[108],"assignment.":[110],"context":[114],"switches":[115],"leading":[116],"to":[117,127,161],"evaluating":[122],"penalty":[125],"due":[126],"limited":[129],"used":[138],"estimating":[140],"performance.":[142],"proposed":[144],"has":[146],"been":[147],"validated":[148],"several":[150],"benchmarks":[151],"over":[152],"range":[154],"comparing":[158],"our":[159],"estimates":[160],"results":[163],"obtained":[164],"from":[165],"standard":[166],"simulation":[167],"tools.":[168],"include":[171],"ARM7TDMI,":[172],"LEON":[173],"Trimedia":[175],"(TM-1000).":[176]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}