{"id":"https://openalex.org/W2158711612","doi":"https://doi.org/10.1109/dsd.2002.1115379","title":"Improving mW/MHz ratio in FPGAs pipelined designs","display_name":"Improving mW/MHz ratio in FPGAs pipelined designs","publication_year":2003,"publication_date":"2003-06-26","ids":{"openalex":"https://openalex.org/W2158711612","doi":"https://doi.org/10.1109/dsd.2002.1115379","mag":"2158711612"},"language":"en","primary_location":{"id":"doi:10.1109/dsd.2002.1115379","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2002.1115379","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025811150","display_name":"Oswaldo Cadenas","orcid":"https://orcid.org/0000-0003-4152-6458"},"institutions":[{"id":"https://openalex.org/I71052956","display_name":"University of Reading","ror":"https://ror.org/05v62cm79","country_code":"GB","type":"education","lineage":["https://openalex.org/I71052956"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"O. Cadenas","raw_affiliation_strings":["School of Computer Science, Cybernetics and Electronic Engineering, University of Reading, UK"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, Cybernetics and Electronic Engineering, University of Reading, UK","institution_ids":["https://openalex.org/I71052956"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051333590","display_name":"Graham M. Megson","orcid":null},"institutions":[{"id":"https://openalex.org/I71052956","display_name":"University of Reading","ror":"https://ror.org/05v62cm79","country_code":"GB","type":"education","lineage":["https://openalex.org/I71052956"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"G. Megson","raw_affiliation_strings":["School of Computer Science, Cybernetics and Electronic Engineering, University of Reading, UK"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, Cybernetics and Electronic Engineering, University of Reading, UK","institution_ids":["https://openalex.org/I71052956"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5025811150"],"corresponding_institution_ids":["https://openalex.org/I71052956"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.21763469,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"15","issue":null,"first_page":"276","last_page":"282"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8268567323684692},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7787746787071228},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.7660783529281616},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.6254537105560303},{"id":"https://openalex.org/keywords/simple","display_name":"Simple (philosophy)","score":0.5997850298881531},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5747840404510498},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.5510830283164978},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.5493009090423584},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.46229666471481323},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4594060480594635},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3981472849845886},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3543508052825928},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12068003416061401},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11963996291160583},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1073046326637268},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.10541260242462158}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8268567323684692},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7787746787071228},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.7660783529281616},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.6254537105560303},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.5997850298881531},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5747840404510498},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.5510830283164978},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.5493009090423584},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.46229666471481323},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4594060480594635},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3981472849845886},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3543508052825928},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12068003416061401},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11963996291160583},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1073046326637268},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.10541260242462158},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/dsd.2002.1115379","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2002.1115379","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","raw_type":"proceedings-article"},{"id":"pmh:oai:centaur.reading.ac.uk:18887","is_oa":false,"landing_page_url":"http://centaur.reading.ac.uk/18887/","pdf_url":null,"source":{"id":"https://openalex.org/S4306402273","display_name":"CentAUR (University of Reading)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I71052956","host_organization_name":"University of Reading","host_organization_lineage":["https://openalex.org/I71052956"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Conference or Workshop Item"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.75,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1514189495","https://openalex.org/W1523176169","https://openalex.org/W1555915743","https://openalex.org/W1588594383","https://openalex.org/W2002533296","https://openalex.org/W2017369466","https://openalex.org/W2078268640","https://openalex.org/W2115250772","https://openalex.org/W2128257312","https://openalex.org/W2140267785","https://openalex.org/W2142612120","https://openalex.org/W2171591485","https://openalex.org/W6635219794"],"related_works":["https://openalex.org/W2544043553","https://openalex.org/W2546284597","https://openalex.org/W2348562861","https://openalex.org/W2170552397","https://openalex.org/W2540393334","https://openalex.org/W2390042878","https://openalex.org/W2062932566","https://openalex.org/W2085828379","https://openalex.org/W2271847574","https://openalex.org/W2017144313"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,14,54,70,110],"simple":[4,55,71],"clocking":[5,75,121],"technique":[6,66,94],"to":[7,13,114],"migrate":[8],"classical":[9],"synchronous":[10,15],"pipelined":[11,27],"designs":[12,103],"functional-equivalent":[16],"alternative":[17],"system":[18],"in":[19,45,67],"the":[20,25,31,35,74,78,92,115,118],"context":[21],"of":[22,34,73,101],"FPGAs.":[23],"When":[24],"new":[26,111],"design":[28,61,84,113],"runs":[29],"at":[30],"same":[32],"throughput":[33],"original":[36],"design,":[37],"around":[38],"30%":[39],"better":[40],"mW/MHz":[41],"ratio":[42],"was":[43],"observed":[44],"Virtex-based":[46],"FPGA":[47],"circuits.":[48],"The":[49,65,88],"evaluation":[50],"is":[51,69,86],"done":[52],"using":[53,117],"but":[56],"representative":[57],"and":[58,98],"practical":[59],"systolic":[60],"as":[62],"an":[63],"example.":[64],"essence":[68],"replacement":[72],"mechanism":[76],"for":[77],"pipe-storage":[79],"elements;":[80],"however":[81],"no":[82],"extra":[83],"effort":[85],"needed.":[87],"results":[89],"show":[90],"that":[91],"proposed":[93],"allows":[95],"immediate":[96],"power":[97],"area-time":[99],"savings":[100],"existing":[102],"rather":[104],"than":[105],"exploring":[106],"potential":[107],"benefits":[108],"by":[109],"logic":[112],"problem":[116],"classic":[119],"pipeline":[120],"mechanism.":[122]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
