{"id":"https://openalex.org/W2098653804","doi":"https://doi.org/10.1109/dsd.2002.1115367","title":"Using formal tools to study complex circuits behaviour","display_name":"Using formal tools to study complex circuits behaviour","publication_year":2003,"publication_date":"2003-06-26","ids":{"openalex":"https://openalex.org/W2098653804","doi":"https://doi.org/10.1109/dsd.2002.1115367","mag":"2098653804"},"language":"en","primary_location":{"id":"doi:10.1109/dsd.2002.1115367","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2002.1115367","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038576947","display_name":"Pierre\u2010Olivier Amblard","orcid":"https://orcid.org/0000-0002-7695-7728"},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"P. Amblard","raw_affiliation_strings":["TIMA/CMP, France","TIMA - Techniques de l'Informatique et de la Micro\u00e9lectronique pour l'Architecture des syst\u00e8mes int\u00e9gr\u00e9s (46 avenue F\u00e9lix Viallet\r\n38031 GRENOBLE Cedex 1 - France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TIMA/CMP, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"TIMA - Techniques de l'Informatique et de la Micro\u00e9lectronique pour l'Architecture des syst\u00e8mes int\u00e9gr\u00e9s (46 avenue F\u00e9lix Viallet\r\n38031 GRENOBLE Cedex 1 - France)","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052843965","display_name":"F. Lagnier","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156361","display_name":"Verimag","ror":"https://ror.org/05afmzm11","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210156361","https://openalex.org/I4210159245","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"F. Lagnier","raw_affiliation_strings":["V\u00e8rimag, Gieres, France","VERIMAG - IMAG - VERIMAG (Verimag\r\nB\u00e2timent IMAG\r\nUniversit\u00e9 Grenoble Alpes\r\n700, avenue centrale\r\n38401 Saint Martin d\u2019H\u00e8res\r\nFrance  - France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"V\u00e8rimag, Gieres, France","institution_ids":["https://openalex.org/I4210156361"]},{"raw_affiliation_string":"VERIMAG - IMAG - VERIMAG (Verimag\r\nB\u00e2timent IMAG\r\nUniversit\u00e9 Grenoble Alpes\r\n700, avenue centrale\r\n38401 Saint Martin d\u2019H\u00e8res\r\nFrance  - France)","institution_ids":["https://openalex.org/I4210156361","https://openalex.org/I899635006"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110001501","display_name":"M. L\u00e9vy","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"M. Levy","raw_affiliation_strings":["LSR-IMAG, France","LSR - IMAG - Laboratoire Logiciels Syst\u00e8mes R\u00e9seaux (681, rue de la Passerelle - BP 72 - 38402 Saint Martin d'H\u00e8res Cedex - France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LSR-IMAG, France","institution_ids":[]},{"raw_affiliation_string":"LSR - IMAG - Laboratoire Logiciels Syst\u00e8mes R\u00e9seaux (681, rue de la Passerelle - BP 72 - 38402 Saint Martin d'H\u00e8res Cedex - France)","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.14782036,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"180","last_page":"186"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7957078218460083},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.6900148987770081},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.6455463767051697},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5857003927230835},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.5762609243392944},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5519808530807495},{"id":"https://openalex.org/keywords/simple","display_name":"Simple (philosophy)","score":0.5351558327674866},{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.5180171132087708},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5118776559829712},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.5114668607711792},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.49419525265693665},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.4825279414653778},{"id":"https://openalex.org/keywords/formal-methods","display_name":"Formal methods","score":0.4352293312549591},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.4133712351322174},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.388290673494339},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3092080354690552},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2711374759674072},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2429245412349701},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1095336377620697}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7957078218460083},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.6900148987770081},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.6455463767051697},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5857003927230835},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.5762609243392944},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5519808530807495},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.5351558327674866},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.5180171132087708},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5118776559829712},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.5114668607711792},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.49419525265693665},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.4825279414653778},{"id":"https://openalex.org/C75606506","wikidata":"https://www.wikidata.org/wiki/Q1049183","display_name":"Formal methods","level":2,"score":0.4352293312549591},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.4133712351322174},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.388290673494339},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3092080354690552},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2711374759674072},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2429245412349701},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1095336377620697},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/dsd.2002.1115367","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2002.1115367","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-00017372v1","is_oa":false,"landing_page_url":"https://hal.science/hal-00017372","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Proceedings-Euromicro-Symposium-on-Digital-System-Design.-Architectures,-Methods-and-Tools., 2002, Dortmund, Germany. pp.180-6, &#x27E8;10.1109/DSD.2002.1115367&#x27E9;","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W28018973","https://openalex.org/W808711452","https://openalex.org/W1547100201","https://openalex.org/W1594229653","https://openalex.org/W1598047736","https://openalex.org/W1828698680","https://openalex.org/W1875492031","https://openalex.org/W1973456473","https://openalex.org/W2016079448","https://openalex.org/W2097465082","https://openalex.org/W2101159578","https://openalex.org/W2125415493","https://openalex.org/W2151250735","https://openalex.org/W2162103377","https://openalex.org/W2188814609","https://openalex.org/W4206455946","https://openalex.org/W4299821709","https://openalex.org/W6996063827"],"related_works":["https://openalex.org/W1965850601","https://openalex.org/W2978427427","https://openalex.org/W161255303","https://openalex.org/W1544097700","https://openalex.org/W2386022279","https://openalex.org/W2243536805","https://openalex.org/W142017057","https://openalex.org/W1488573418","https://openalex.org/W2152752131","https://openalex.org/W1702800398"],"abstract_inverted_index":{"We":[0],"use":[1],"a":[2,46],"formal":[3],"tool":[4],"to":[5,34,59],"extract":[6],"Finite":[7],"State":[8],"Machines":[9],"(FSM)":[10],"based":[11],"representations":[12,30],"(lists":[13],"of":[14,18,39],"states":[15],"and":[16,24,28,74],"transitions)":[17],"sequential":[19],"circuits":[20],"described":[21],"by":[22],"flip-flops":[23],"gates.":[25],"These":[26],"complete":[27],"optimized":[29],"help":[31],"the":[32,36,40],"designer":[33],"understand":[35],"accurate":[37],"behaviour":[38],"circuit.":[41],"This":[42,63],"deep":[43],"understanding":[44],"is":[45,56],"prerequisite":[47],"for":[48],"any":[49],"verification":[50],"or":[51],"test":[52],"process.":[53],"An":[54],"example":[55],"fully":[57],"presented":[58],"illustrate":[60],"our":[61,69],"method.":[62],"simple":[64],"pipelined":[65],"processor":[66],"comes":[67],"from":[68],"experience":[70],"in":[71],"computer":[72],"architecture":[73],"digital":[75],"design":[76],"education.":[77]},"counts_by_year":[],"updated_date":"2026-07-02T09:51:11.867554","created_date":"2025-10-10T00:00:00"}
