{"id":"https://openalex.org/W4237014338","doi":"https://doi.org/10.1109/dsd.2002.1115364","title":"Implementation of a streaming execution unit","display_name":"Implementation of a streaming execution unit","publication_year":2003,"publication_date":"2003-06-26","ids":{"openalex":"https://openalex.org/W4237014338","doi":"https://doi.org/10.1109/dsd.2002.1115364"},"language":"en","primary_location":{"id":"doi:10.1109/dsd.2002.1115364","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2002.1115364","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074548804","display_name":"D. Cheresiz","orcid":null},"institutions":[{"id":"https://openalex.org/I121797337","display_name":"Leiden University","ror":"https://ror.org/027bh9e22","country_code":"NL","type":"education","lineage":["https://openalex.org/I121797337"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"D. Cheresiz","raw_affiliation_strings":["Leiden Institute of Advanced Computer Science, Leiden University, Leiden, Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Leiden Institute of Advanced Computer Science, Leiden University, Leiden, Netherlands","institution_ids":["https://openalex.org/I121797337"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081583238","display_name":"B. Juurlink","orcid":null},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"B. Juurlink","raw_affiliation_strings":["Computer Engineering Laboratory, Delft University of Technnology, Delft, Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering Laboratory, Delft University of Technnology, Delft, Netherlands","institution_ids":["https://openalex.org/I98358874"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065080706","display_name":"S. Vassiliadis","orcid":null},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"S. Vassiliadis","raw_affiliation_strings":["Computer Engineering Laboratory, Delft University of Technnology, Delft, Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering Laboratory, Delft University of Technnology, Delft, Netherlands","institution_ids":["https://openalex.org/I98358874"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5048188291","display_name":"H.A.G. Wijshoff","orcid":null},"institutions":[{"id":"https://openalex.org/I121797337","display_name":"Leiden University","ror":"https://ror.org/027bh9e22","country_code":"NL","type":"education","lineage":["https://openalex.org/I121797337"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"H.A.G. Wijshoff","raw_affiliation_strings":["Leiden Institute of Advanced Computer Science, Leiden University, Leiden, Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Leiden Institute of Advanced Computer Science, Leiden University, Leiden, Netherlands","institution_ids":["https://openalex.org/I121797337"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.33121597,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"156","last_page":"164"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8780345916748047},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.7842864394187927},{"id":"https://openalex.org/keywords/mmx","display_name":"MMX","score":0.7425748705863953},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6671020984649658},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5488638281822205},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4587474465370178},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42505139112472534},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.386263906955719},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3803115785121918},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3298180401325226},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.26019227504730225},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1052333414554596}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8780345916748047},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.7842864394187927},{"id":"https://openalex.org/C85918911","wikidata":"https://www.wikidata.org/wiki/Q904336","display_name":"MMX","level":2,"score":0.7425748705863953},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6671020984649658},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5488638281822205},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4587474465370178},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42505139112472534},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.386263906955719},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3803115785121918},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3298180401325226},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.26019227504730225},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1052333414554596}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dsd.2002.1115364","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2002.1115364","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1555915743","https://openalex.org/W2005128309","https://openalex.org/W2021488422","https://openalex.org/W2099924222","https://openalex.org/W2134080755","https://openalex.org/W2137952821","https://openalex.org/W2143740079","https://openalex.org/W2155430240","https://openalex.org/W2165964351","https://openalex.org/W4237223070","https://openalex.org/W4237433798"],"related_works":["https://openalex.org/W1534961658","https://openalex.org/W2544823983","https://openalex.org/W35209463","https://openalex.org/W2377044310","https://openalex.org/W2265644042","https://openalex.org/W2542148463","https://openalex.org/W2329607239","https://openalex.org/W3151470456","https://openalex.org/W1595089495","https://openalex.org/W1480874568"],"abstract_inverted_index":{"The":[0],"Complex":[1],"Streamed":[2],"Instruction":[3],"(CSI)":[4],"set":[5],"is":[6,78,88],"an":[7],"ISA":[8,51],"extension":[9],"targeted":[10],"at":[11],"multimedia":[12],"applications.":[13],"CSI":[14,43,70],"instructions":[15,71],"process":[16],"two-dimensional":[17],"data":[18,25,32,83],"streams":[19],"stored":[20],"in":[21,35,99],"memory,":[22],"performing":[23],"sectioning,":[24],"alignment":[26],"and":[27,56,103,112],"conversion":[28],"between":[29],"different":[30],"packed":[31],"types":[33],"all":[34],"hardware.":[36],"It":[37],"has":[38],"been":[39],"shown":[40,89],"previously":[41],"that":[42,67,75,90],"provides":[44],"significant":[45],"speedups":[46],"compared":[47],"to":[48],"current":[49],"media":[50],"extensions":[52],"such":[53],"as":[54],"MMX":[55],"VIS.":[57],"This":[58],"paper":[59],"presents":[60],"a":[61,65,100,106],"detailed":[62],"design":[63],"of":[64],"unit":[66,77],"can":[68,96],"execute":[69],"under":[72],"the":[73,76,81,91],"assumption":[74],"interfaced":[79],"with":[80,109],"L1":[82],"cache.":[84],"In":[85],"particular":[86],"it":[87],"complex,":[92],"two-dimensional,":[93],"address-generation":[94],"calculations":[95],"be":[97],"performed":[98],"pipelined":[101],"fashion":[102],"implemented":[104],"using":[105],"three-stage":[107],"pipeline":[108],"acceptable":[110],"delay":[111],"hardware":[113],"cost.":[114]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}