{"id":"https://openalex.org/W2127180541","doi":"https://doi.org/10.1109/dsd.2002.1115354","title":"The synthesis of a hardware scheduler for non-manifest loops","display_name":"The synthesis of a hardware scheduler for non-manifest loops","publication_year":2003,"publication_date":"2003-06-26","ids":{"openalex":"https://openalex.org/W2127180541","doi":"https://doi.org/10.1109/dsd.2002.1115354","mag":"2127180541"},"language":"en","primary_location":{"id":"doi:10.1109/dsd.2002.1115354","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2002.1115354","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://ris.utwente.nl/ws/files/5452854/dsd2002_mansour_o.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037889399","display_name":"Omar Mansour","orcid":"https://orcid.org/0009-0007-3325-4516"},"institutions":[{"id":"https://openalex.org/I94624287","display_name":"University of Twente","ror":"https://ror.org/006hf6230","country_code":"NL","type":"education","lineage":["https://openalex.org/I94624287"]}],"countries":["NL"],"is_corresponding":true,"raw_author_name":"O. Mansour","raw_affiliation_strings":["Department of Computer Science, University of Twente, Enschede, Netherlands","Dept. of Comput. Sci., Twente Univ., Enschede, Netherlands"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Twente, Enschede, Netherlands","institution_ids":["https://openalex.org/I94624287"]},{"raw_affiliation_string":"Dept. of Comput. Sci., Twente Univ., Enschede, Netherlands","institution_ids":["https://openalex.org/I94624287"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085496906","display_name":"Egbert Molenkamp","orcid":null},"institutions":[{"id":"https://openalex.org/I94624287","display_name":"University of Twente","ror":"https://ror.org/006hf6230","country_code":"NL","type":"education","lineage":["https://openalex.org/I94624287"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"E. Molenkamp","raw_affiliation_strings":["Department of Computer Science, University of Twente, Enschede, Netherlands","Dept. of Comput. Sci., Twente Univ., Enschede, Netherlands"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Twente, Enschede, Netherlands","institution_ids":["https://openalex.org/I94624287"]},{"raw_affiliation_string":"Dept. of Comput. Sci., Twente Univ., Enschede, Netherlands","institution_ids":["https://openalex.org/I94624287"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110226558","display_name":"Thijs Krol","orcid":null},"institutions":[{"id":"https://openalex.org/I94624287","display_name":"University of Twente","ror":"https://ror.org/006hf6230","country_code":"NL","type":"education","lineage":["https://openalex.org/I94624287"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"T. Krol","raw_affiliation_strings":["Department of Computer Science, University of Twente, Enschede, Netherlands","Dept. of Comput. Sci., Twente Univ., Enschede, Netherlands"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Twente, Enschede, Netherlands","institution_ids":["https://openalex.org/I94624287"]},{"raw_affiliation_string":"Dept. of Comput. Sci., Twente Univ., Enschede, Netherlands","institution_ids":["https://openalex.org/I94624287"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5037889399"],"corresponding_institution_ids":["https://openalex.org/I94624287"],"apc_list":null,"apc_paid":null,"fwci":0.4952,"has_fulltext":true,"cited_by_count":2,"citation_normalized_percentile":{"value":0.67043966,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"19","issue":null,"first_page":"78","last_page":"85"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.840644121170044},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.6902985572814941},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.6116631031036377},{"id":"https://openalex.org/keywords/dynamic-priority-scheduling","display_name":"Dynamic priority scheduling","score":0.593881368637085},{"id":"https://openalex.org/keywords/fixed-priority-pre-emptive-scheduling","display_name":"Fixed-priority pre-emptive scheduling","score":0.5375816822052002},{"id":"https://openalex.org/keywords/processor-scheduling","display_name":"Processor scheduling","score":0.5295346975326538},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.5152568817138672},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.47892579436302185},{"id":"https://openalex.org/keywords/two-level-scheduling","display_name":"Two-level scheduling","score":0.46741557121276855},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.44524237513542175},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4292398691177368},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.40965571999549866},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3974493145942688},{"id":"https://openalex.org/keywords/rate-monotonic-scheduling","display_name":"Rate-monotonic scheduling","score":0.3120996952056885},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.27089405059814453},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1845080554485321},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.08876058459281921}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.840644121170044},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.6902985572814941},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.6116631031036377},{"id":"https://openalex.org/C107568181","wikidata":"https://www.wikidata.org/wiki/Q5319000","display_name":"Dynamic priority scheduling","level":3,"score":0.593881368637085},{"id":"https://openalex.org/C122141398","wikidata":"https://www.wikidata.org/wiki/Q5456330","display_name":"Fixed-priority pre-emptive scheduling","level":5,"score":0.5375816822052002},{"id":"https://openalex.org/C2984822820","wikidata":"https://www.wikidata.org/wiki/Q1123036","display_name":"Processor scheduling","level":3,"score":0.5295346975326538},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.5152568817138672},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47892579436302185},{"id":"https://openalex.org/C119948110","wikidata":"https://www.wikidata.org/wiki/Q7858726","display_name":"Two-level scheduling","level":4,"score":0.46741557121276855},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.44524237513542175},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4292398691177368},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.40965571999549866},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3974493145942688},{"id":"https://openalex.org/C127456818","wikidata":"https://www.wikidata.org/wiki/Q238879","display_name":"Rate-monotonic scheduling","level":4,"score":0.3120996952056885},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.27089405059814453},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1845080554485321},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.08876058459281921},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":5,"locations":[{"id":"doi:10.1109/dsd.2002.1115354","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2002.1115354","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","raw_type":"proceedings-article"},{"id":"pmh:oai:ris.utwente.nl:publications/5ee72295-52a7-4c38-ae6d-db18bccff872","is_oa":true,"landing_page_url":"https://research.utwente.nl/en/publications/5ee72295-52a7-4c38-ae6d-db18bccff872","pdf_url":"https://ris.utwente.nl/ws/files/5452854/dsd2002_mansour_o.pdf","source":{"id":"https://openalex.org/S4406922991","display_name":"University of Twente Research Information","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Mansour, O, Molenkamp, E & Krol, T 2002, The Synthesis of a Hardware Scheduler for Non-Manifest Loops. in Euromicro Symposium on Digital System Design (DSD'02). IEEE, pp. 78-85, 5th EUROMICRO Symposium on Digital System Design, DSD 2002, Dortmund, Germany, 4/09/02. https://doi.org/10.1109/DSD.2002.1115354","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.110.409","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.110.409","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://doc.utwente.nl/38172/1/01115354.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.133.2318","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.133.2318","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://eprints.eemcs.utwente.nl/2720/01/dsd2002_mansour_o.pdf","raw_type":"text"},{"id":"pmh:oai:ris.utwente.nl:publications/5ee72295-52a7-4c38-ae6d-db18bccff872","is_oa":false,"landing_page_url":"http://doi.ieeecomputersociety.org/10.1109/DSD.2002.1115354","pdf_url":null,"source":{"id":"https://openalex.org/S4406922991","display_name":"University of Twente Research Information","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Mansour , O , Molenkamp , E &amp; Krol , T 2002 , The Synthesis of a Hardware Scheduler for Non-Manifest Loops . in Euromicro Symposium on Digital System Design (DSD'02) . IEEE , pp. 78-85 , 5th EUROMICRO Symposium on Digital System Design, DSD 2002 , Dortmund , Germany , 4/09/02 . https://doi.org/10.1109/DSD.2002.1115354","raw_type":"contributionToPeriodical"}],"best_oa_location":{"id":"pmh:oai:ris.utwente.nl:publications/5ee72295-52a7-4c38-ae6d-db18bccff872","is_oa":true,"landing_page_url":"https://research.utwente.nl/en/publications/5ee72295-52a7-4c38-ae6d-db18bccff872","pdf_url":"https://ris.utwente.nl/ws/files/5452854/dsd2002_mansour_o.pdf","source":{"id":"https://openalex.org/S4406922991","display_name":"University of Twente Research Information","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Mansour, O, Molenkamp, E & Krol, T 2002, The Synthesis of a Hardware Scheduler for Non-Manifest Loops. in Euromicro Symposium on Digital System Design (DSD'02). IEEE, pp. 78-85, 5th EUROMICRO Symposium on Digital System Design, DSD 2002, Dortmund, Germany, 4/09/02. https://doi.org/10.1109/DSD.2002.1115354","raw_type":"info:eu-repo/semantics/publishedVersion"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2127180541.pdf","grobid_xml":"https://content.openalex.org/works/W2127180541.grobid-xml"},"referenced_works_count":11,"referenced_works":["https://openalex.org/W1567363020","https://openalex.org/W1581247463","https://openalex.org/W1603495093","https://openalex.org/W2139981206","https://openalex.org/W2155783364","https://openalex.org/W2169281837","https://openalex.org/W2493328864","https://openalex.org/W4240901955","https://openalex.org/W6634542754","https://openalex.org/W6636093136","https://openalex.org/W6684999513"],"related_works":["https://openalex.org/W1545991362","https://openalex.org/W2545511463","https://openalex.org/W3184267879","https://openalex.org/W2167574351","https://openalex.org/W2184166483","https://openalex.org/W2257422103","https://openalex.org/W2106332846","https://openalex.org/W4300092030","https://openalex.org/W2978148977","https://openalex.org/W1526709096"],"abstract_inverted_index":{"This":[0,89],"paper":[1,51],"addresses":[2],"the":[3,38,70,87],"hardware":[4],"implementation":[5],"of":[6,86],"a":[7,45,52,64],"dynamic":[8,53],"scheduler":[9],"for":[10,27],"non-manifest":[11,33],"data":[12],"dependent":[13],"periodic":[14],"loops.":[15],"Static":[16],"scheduling":[17,32,54],"techniques":[18],"which":[19,43],"are":[20],"known":[21],"to":[22,58],"give":[23],"near":[24],"optimal":[25],"scheduling-solutions":[26],"manifest":[28],"loops,":[29,34],"fail":[30],"at":[31],"since":[35],"they":[36],"lack":[37],"run":[39],"time":[40],"information":[41],"needed":[42],"makes":[44],"static":[46],"schedule":[47],"feasible.":[48],"In":[49],"this":[50,60],"approach":[55],"was":[56],"chosen":[57],"circumvent":[59],"problem.":[61],"We":[62],"present":[63],"case":[65],"study":[66],"using":[67],"VHDL":[68],"where":[69],"focus":[71],"lies":[72],"on":[73],"implementations":[74],"with":[75],"minimal":[76],"memory":[77],"usage":[78],"and":[79,95],"low":[80],"communication":[81],"overhead":[82],"between":[83],"various":[84],"components":[85],"architecture.":[88],"has":[90],"resulted":[91],"in":[92],"an":[93],"efficient":[94],"synthesisable":[96],"system.":[97]},"counts_by_year":[],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
