{"id":"https://openalex.org/W2123580658","doi":"https://doi.org/10.1109/dsd.2002.1115345","title":"An asynchronous victim cache","display_name":"An asynchronous victim cache","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2123580658","doi":"https://doi.org/10.1109/dsd.2002.1115345","mag":"2123580658"},"language":"en","primary_location":{"id":"doi:10.1109/dsd.2002.1115345","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2002.1115345","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103160326","display_name":"Daranee Hormdee","orcid":"https://orcid.org/0009-0008-2192-5703"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"D. Hormdee","raw_affiliation_strings":["Department of Computer Science, University of Manchester, Institute of Science and Technology, Manchester, UK","Dept. of Comput. Sci., Manchester Univ., UK#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Manchester, Institute of Science and Technology, Manchester, UK","institution_ids":["https://openalex.org/I28407311"]},{"raw_affiliation_string":"Dept. of Comput. Sci., Manchester Univ., UK#TAB#","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053098822","display_name":"Jim Garside","orcid":"https://orcid.org/0000-0001-8812-4742"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"J.D. Garside","raw_affiliation_strings":["Department of Computer Science, University of Manchester, Institute of Science and Technology, Manchester, UK","Dept. of Comput. Sci., Manchester Univ., UK#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Manchester, Institute of Science and Technology, Manchester, UK","institution_ids":["https://openalex.org/I28407311"]},{"raw_affiliation_string":"Dept. of Comput. Sci., Manchester Univ., UK#TAB#","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5083177159","display_name":"Steve Furber","orcid":"https://orcid.org/0000-0002-6524-3367"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"S.B. Furber","raw_affiliation_strings":["Department of Computer Science, University of Manchester, Institute of Science and Technology, Manchester, UK","Dept. of Comput. Sci., Manchester Univ., UK#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Manchester, Institute of Science and Technology, Manchester, UK","institution_ids":["https://openalex.org/I28407311"]},{"raw_affiliation_string":"Dept. of Comput. Sci., Manchester Univ., UK#TAB#","institution_ids":["https://openalex.org/I28407311"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I28407311"],"apc_list":null,"apc_paid":null,"fwci":0.4649,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.60267047,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"4","last_page":"11"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8827523589134216},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.792496383190155},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7236642837524414},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.6839707493782043},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.6797052025794983},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.6255444288253784},{"id":"https://openalex.org/keywords/cache-invalidation","display_name":"Cache invalidation","score":0.6097790002822876},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.6055544018745422},{"id":"https://openalex.org/keywords/bus-sniffing","display_name":"Bus sniffing","score":0.49039340019226074},{"id":"https://openalex.org/keywords/page-cache","display_name":"Page cache","score":0.4663962721824646},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.45117348432540894},{"id":"https://openalex.org/keywords/mesi-protocol","display_name":"MESI protocol","score":0.45089247822761536},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42944595217704773},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4231451451778412},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41955995559692383},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.374298095703125},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.27079591155052185}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8827523589134216},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.792496383190155},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7236642837524414},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.6839707493782043},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.6797052025794983},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.6255444288253784},{"id":"https://openalex.org/C25536678","wikidata":"https://www.wikidata.org/wiki/Q5015977","display_name":"Cache invalidation","level":5,"score":0.6097790002822876},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.6055544018745422},{"id":"https://openalex.org/C51185590","wikidata":"https://www.wikidata.org/wiki/Q1017228","display_name":"Bus sniffing","level":5,"score":0.49039340019226074},{"id":"https://openalex.org/C36340418","wikidata":"https://www.wikidata.org/wiki/Q7124288","display_name":"Page cache","level":5,"score":0.4663962721824646},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.45117348432540894},{"id":"https://openalex.org/C120936851","wikidata":"https://www.wikidata.org/wiki/Q1408065","display_name":"MESI protocol","level":5,"score":0.45089247822761536},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42944595217704773},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4231451451778412},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41955995559692383},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.374298095703125},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.27079591155052185}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/dsd.2002.1115345","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2002.1115345","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.678.193","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.678.193","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://apt.cs.manchester.ac.uk/ftp/pub/apt/papers/ying_dsd02.pdf","raw_type":"text"},{"id":"pmh:oai:pure.atira.dk:openaire_cris_publications/3be9c4a6-9683-41d2-85b5-1ec34db86618","is_oa":false,"landing_page_url":"https://research.manchester.ac.uk/en/publications/3be9c4a6-9683-41d2-85b5-1ec34db86618","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Hormdee, D, Garside, J & Furber, S B 2002, An Asynchronous Victim Cache. in Proceedings Euromicro Symposium on Digital System Design. IEEE Computer Society , pp. 4-11, 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany, 1/01/24. https://doi.org/10.1109/DSD.2002.1115345","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:pure.atira.dk:publications/3be9c4a6-9683-41d2-85b5-1ec34db86618","is_oa":false,"landing_page_url":"http://dblp.uni-trier.de/rec/bibtex/conf/dsd/HormdeeGF02","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":"public-domain","license_id":"https://openalex.org/licenses/public-domain","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Hormdee, D, Garside, J & Furber, S B 2002, An Asynchronous Victim Cache. in Proceedings Euromicro Symposium on Digital System Design. IEEE Computer Society , pp. 4-11, 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany, 1/01/24. https://doi.org/10.1109/DSD.2002.1115345","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.800000011920929,"id":"https://metadata.un.org/sdg/16","display_name":"Peace, Justice and strong institutions"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1555915743","https://openalex.org/W2100589405","https://openalex.org/W2104105510","https://openalex.org/W2123021615","https://openalex.org/W2132339613","https://openalex.org/W2138000055","https://openalex.org/W2143285027","https://openalex.org/W2150054527","https://openalex.org/W2154346069","https://openalex.org/W2154622477","https://openalex.org/W2163820265","https://openalex.org/W2725179571","https://openalex.org/W2739649174","https://openalex.org/W2911717499","https://openalex.org/W4237150160","https://openalex.org/W4250613128","https://openalex.org/W6633127185","https://openalex.org/W6677348501","https://openalex.org/W6680056528","https://openalex.org/W6683865707"],"related_works":["https://openalex.org/W4312759433","https://openalex.org/W2290179447","https://openalex.org/W4304166325","https://openalex.org/W273173017","https://openalex.org/W2184371594","https://openalex.org/W2148571123","https://openalex.org/W2165666031","https://openalex.org/W4321259568","https://openalex.org/W2152423944","https://openalex.org/W2801630946"],"abstract_inverted_index":{"Memory":[0],"bandwidth":[1],"is":[2,12,35,74,98,100,111,155,164],"a":[3,16,57,103,123,141,148,167,182,189,197,209],"limiting":[4],"factor":[5],"with":[6],"many":[7],"modem":[8],"microprocessors":[9],"and":[10],"it":[11,110,137],"usual":[13],"to":[14,18,66,139,161,170,185],"include":[15],"cache":[17,30,84,115,184,204],"reduce":[19],"the":[20,26,32,38,54,61,67,82,95,114,127,159,171,207,215],"amount":[21],"of":[22,46,56,63,76,126,129,200,214],"memory":[23,144],"traffic.":[24],"Of":[25],"two":[27],"commonly":[28],"used":[29],"write-policies,":[31],"copy-back":[33,203],"approach":[34,40],"better":[36],"than":[37],"write-through":[39],"in":[41,60,151,166,188],"this":[42,72],"respect.":[43],"The":[44,193],"performance":[45],"both":[47],"approaches":[48],"can":[49],"be":[50,118,134,162],"further":[51],"aided":[52],"by":[53],"inclusion":[55],"small":[58],"buffer":[59,73,96],"path":[62],"outgoing":[64],"writes":[65],"main":[68,83],"memory,":[69],"especially":[70],"if":[71,85,136],"capable":[75],"forwarding":[77,149,187],"its":[78],"contents":[79],"back":[80],"into":[81],"they":[86,91],"are":[87,92],"needed":[88],"again":[89],"before":[90],"emptied":[93],"from":[94],"This":[97,176],"what":[99],"known":[101],"as":[102,120],"victim":[104,183],"cache.":[105],"For":[106],"an":[107,130,152,179,201],"asynchronous":[108,119,131,153,191,202,212],"microprocessor":[109,132],"logical":[112],"that":[113],"system":[116,154,205],"should":[117],"well;":[121],"since":[122],"large":[124],"degree":[125],"flexibility":[128],"would":[133],"lost":[135],"were":[138],"use":[140],"standard":[142],"synchronous":[143],"interface.":[145],"However":[146],"implementing":[147],"mechanism":[150],"more":[156],"difficult":[157],"because":[158],"data":[160],"forwarded":[163],"flowing":[165],"manner":[168],"unsynchronised":[169],"process":[172],"which":[173],"requires":[174],"it.":[175],"paper":[177],"presents":[178],"architecture":[180],"for":[181,206],"resolve":[186],"totally":[190],"environment.":[192],"resultant":[194],"structure":[195],"forms":[196],"key":[198],"part":[199],"Amulet3,":[208],"third":[210],"generation":[211],"implementation":[213],"ARM":[216],"processor.":[217]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}