{"id":"https://openalex.org/W4292388257","doi":"https://doi.org/10.1109/drc55272.2022.9855650","title":"An Experimentally Validated, Universal Memristor Model Enabling Temporal Neuromorphic Computation","display_name":"An Experimentally Validated, Universal Memristor Model Enabling Temporal Neuromorphic Computation","publication_year":2022,"publication_date":"2022-06-26","ids":{"openalex":"https://openalex.org/W4292388257","doi":"https://doi.org/10.1109/drc55272.2022.9855650"},"language":"en","primary_location":{"id":"doi:10.1109/drc55272.2022.9855650","is_oa":false,"landing_page_url":"https://doi.org/10.1109/drc55272.2022.9855650","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 Device Research Conference (DRC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054692364","display_name":"Bill Zivasatienraj","orcid":"https://orcid.org/0000-0002-0522-4869"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Bill Zivasatienraj","raw_affiliation_strings":["Georgia Institute of Technology,Atlanta,GA,USA,30332"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology,Atlanta,GA,USA,30332","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072792961","display_name":"W. Alan Doolittle","orcid":"https://orcid.org/0000-0001-6427-5327"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"W. Alan Doolittle","raw_affiliation_strings":["Georgia Institute of Technology,Atlanta,GA,USA,30332"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology,Atlanta,GA,USA,30332","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5054692364"],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":0.0915,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.39776963,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10581","display_name":"Neural dynamics and brain function","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2805","display_name":"Cognitive Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.9396033883094788},{"id":"https://openalex.org/keywords/neuromorphic-engineering","display_name":"Neuromorphic engineering","score":0.9021769762039185},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.7336852550506592},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7194994688034058},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.646004319190979},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.6370916366577148},{"id":"https://openalex.org/keywords/von-neumann-architecture","display_name":"Von Neumann architecture","score":0.6015384793281555},{"id":"https://openalex.org/keywords/convolutional-neural-network","display_name":"Convolutional neural network","score":0.4403212070465088},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4402915835380554},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.356461763381958},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.33411741256713867},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3277096748352051},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.30648791790008545},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.17100834846496582},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.14941567182540894},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13023599982261658},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11502096056938171}],"concepts":[{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.9396033883094788},{"id":"https://openalex.org/C151927369","wikidata":"https://www.wikidata.org/wiki/Q1981312","display_name":"Neuromorphic engineering","level":3,"score":0.9021769762039185},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.7336852550506592},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7194994688034058},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.646004319190979},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.6370916366577148},{"id":"https://openalex.org/C80469333","wikidata":"https://www.wikidata.org/wiki/Q189088","display_name":"Von Neumann architecture","level":2,"score":0.6015384793281555},{"id":"https://openalex.org/C81363708","wikidata":"https://www.wikidata.org/wiki/Q17084460","display_name":"Convolutional neural network","level":2,"score":0.4403212070465088},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4402915835380554},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.356461763381958},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.33411741256713867},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3277096748352051},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.30648791790008545},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.17100834846496582},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.14941567182540894},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13023599982261658},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11502096056938171},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/drc55272.2022.9855650","is_oa":false,"landing_page_url":"https://doi.org/10.1109/drc55272.2022.9855650","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 Device Research Conference (DRC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W3007554797","https://openalex.org/W4214576356"],"related_works":["https://openalex.org/W1872623660","https://openalex.org/W3207218810","https://openalex.org/W4292697011","https://openalex.org/W3212508523","https://openalex.org/W1995352804","https://openalex.org/W4386475142","https://openalex.org/W2909534142","https://openalex.org/W2793181810","https://openalex.org/W4367187682","https://openalex.org/W2891417865"],"abstract_inverted_index":{"The":[0],"memristor":[1,84],"has":[2],"been":[3,54],"identified":[4],"as":[5,106,108],"a":[6,83,99],"potential":[7],"solution":[8],"for":[9,63,112],"achieving":[10],"non-von":[11],"Neumann":[12],"computation":[13,111],"due":[14],"to":[15,18,40,49,57,91],"its":[16],"ability":[17],"perform":[19],"computation-in-memory,":[20],"therefore":[21],"bypassing":[22],"the":[23,89,113],"memory":[24,58],"transfer":[25],"bottleneck.":[26],"Many":[27],"memristive":[28,94],"technologies":[29],"have":[30,53],"emerged":[31],"with":[32,88,98],"various":[33,93],"mechanisms":[34],"ranging":[35],"from":[36],"binary":[37],"resistive":[38],"switching":[39],"fully":[41],"analog":[42],"intercalation-based":[43],"memristors.":[44],"However,":[45,71],"application":[46],"of":[47,115],"memristors":[48],"novel":[50],"computing":[51,117],"architectures":[52],"mostly":[55],"limited":[56],"arrays":[59],"and":[60],"multiply-and-accumulate":[61],"functions,":[62],"example":[64],"in":[65],"convolutional":[66],"neural":[67,74],"networks":[68,75],"(CNN)":[69],"[1].":[70],"future":[72],"recurrent":[73],"(RNN)":[76],"must":[77],"implement":[78],"complex":[79],"temporal":[80,110],"dynamics.":[81],"Hence,":[82],"model":[85],"is":[86],"proposed":[87],"versatility":[90],"emulate":[92],"technologies,":[95],"including":[96],"those":[97],"true":[100],"or":[101],"virtual":[102],"dependence":[103],"on":[104],"flux-linkage,":[105],"well":[107],"deploy":[109],"investigation":[114],"new":[116],"architectures.":[118]},"counts_by_year":[{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}