{"id":"https://openalex.org/W2888978443","doi":"https://doi.org/10.1109/drc.2018.8442180","title":"An Improved 1T-DRAM Cell Using TiO<sub>2</sub>as the Source and Drain of an n-Channel PD-SOI MOSFET","display_name":"An Improved 1T-DRAM Cell Using TiO<sub>2</sub>as the Source and Drain of an n-Channel PD-SOI MOSFET","publication_year":2018,"publication_date":"2018-06-01","ids":{"openalex":"https://openalex.org/W2888978443","doi":"https://doi.org/10.1109/drc.2018.8442180","mag":"2888978443"},"language":"en","primary_location":{"id":"doi:10.1109/drc.2018.8442180","is_oa":false,"landing_page_url":"https://doi.org/10.1109/drc.2018.8442180","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 76th Device Research Conference (DRC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5023202619","display_name":"Dibyendu Chatterjee","orcid":"https://orcid.org/0000-0002-9036-2042"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Dibyendu Chatterjee","raw_affiliation_strings":["Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, Maharashtra, India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, Maharashtra, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5042386910","display_name":"Anil Kottantharayil","orcid":"https://orcid.org/0000-0002-5208-1012"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Anil Kottantharayil","raw_affiliation_strings":["Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, Maharashtra, India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, Maharashtra, India","institution_ids":["https://openalex.org/I162827531"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5023202619"],"corresponding_institution_ids":["https://openalex.org/I162827531"],"apc_list":null,"apc_paid":null,"fwci":0.1288,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.48035367,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.9275962710380554},{"id":"https://openalex.org/keywords/mosfet","display_name":"MOSFET","score":0.6658849120140076},{"id":"https://openalex.org/keywords/silicon-on-insulator","display_name":"Silicon on insulator","score":0.6539422869682312},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.5629793405532837},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.4933132231235504},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4849960505962372},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.48166143894195557},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.4642292857170105},{"id":"https://openalex.org/keywords/dynamic-random-access-memory","display_name":"Dynamic random-access memory","score":0.45830774307250977},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.41280776262283325},{"id":"https://openalex.org/keywords/data-retention","display_name":"Data retention","score":0.41101598739624023},{"id":"https://openalex.org/keywords/silicon","display_name":"Silicon","score":0.3749120235443115},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3644554615020752},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.3514038920402527},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18047648668289185},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1377497911453247},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.10714098811149597}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.9275962710380554},{"id":"https://openalex.org/C2778413303","wikidata":"https://www.wikidata.org/wiki/Q210793","display_name":"MOSFET","level":4,"score":0.6658849120140076},{"id":"https://openalex.org/C53143962","wikidata":"https://www.wikidata.org/wiki/Q1478788","display_name":"Silicon on insulator","level":3,"score":0.6539422869682312},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.5629793405532837},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.4933132231235504},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4849960505962372},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.48166143894195557},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.4642292857170105},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.45830774307250977},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.41280776262283325},{"id":"https://openalex.org/C2780866740","wikidata":"https://www.wikidata.org/wiki/Q5227345","display_name":"Data retention","level":2,"score":0.41101598739624023},{"id":"https://openalex.org/C544956773","wikidata":"https://www.wikidata.org/wiki/Q670","display_name":"Silicon","level":2,"score":0.3749120235443115},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3644554615020752},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.3514038920402527},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18047648668289185},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1377497911453247},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.10714098811149597},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/drc.2018.8442180","is_oa":false,"landing_page_url":"https://doi.org/10.1109/drc.2018.8442180","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 76th Device Research Conference (DRC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2020014415","https://openalex.org/W2078494774","https://openalex.org/W2080708629","https://openalex.org/W2087963263","https://openalex.org/W2494487464"],"related_works":["https://openalex.org/W2074922484","https://openalex.org/W2130607063","https://openalex.org/W2063061014","https://openalex.org/W2149227206","https://openalex.org/W2001316072","https://openalex.org/W2473808647","https://openalex.org/W3004383742","https://openalex.org/W2105633922","https://openalex.org/W2540867894","https://openalex.org/W2067914900"],"abstract_inverted_index":{"Due":[0],"to":[1,77],"fabrication":[2],"challenges":[3],"for":[4,51,131,141,172,187,211],"the":[5,8,20,35,45,65,99,105,139,188],"scaling":[6],"of":[7,10,22,37,107,135],"capacitor":[9],"a":[11,75,82,142],"conventional":[12],"DRAM":[13,175],"cell":[14,55,176,196],"below":[15],"100":[16],"nm":[17],"technology":[18],"node,":[19],"concept":[21],"1":[23,53,85,213],"T-DRAM":[24,54,86,214],"cell[I]":[25],"was":[26],"proposed":[27,174,189],"as":[28,44,98,104,160,162],"an":[29,38,108,149,155],"alternative.":[30],"In":[31],"all-Si":[32,52,150,212],"1T-DRAM":[33,151,195],"cell,":[34,87,215],"body":[36,140],"n-channel":[39,109],"PD-SOI":[40],"MOSFET":[41],"is":[42,56,96,129,146,197,217],"used":[43,97],"storage":[46],"node.":[47],"The":[48,183],"biggest":[49],"drawback":[50],"it's":[57],"low":[58],"retention":[59,158,185],"time":[60,144,159,186],"which":[61],"does":[62],"not":[63],"meet":[64],"ITRS":[66],"specification":[67],"(64":[68],"ms":[69,202,219],"at":[70,165,203,223],"358":[71,207],"K)":[72],"[2].":[73],"As":[74],"solution":[76],"this":[78],"problem,":[79],"we":[80],"propose":[81],"novel":[83],"capacitor-less":[84],"where":[88],"intrinsically":[89],"n-type":[90],"TiO":[91,119,190],"<sub":[92,120,191],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[93,121,192],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sub>":[94,122,193],"[3]":[95],"sourceldrain":[100],"material":[101],"and":[102,123,169,200,206,210,220,226],"silicon":[103],"channel":[106],"partially":[110],"depleted":[111],"SOI":[112],"MOSFET.":[113],"Large":[114],"valance":[115],"band":[116],"offset":[117],"between":[118],"Si":[124],"(\u0394EV":[125],"\u2248":[126],"2":[127],"eV)":[128],"utilized":[130],"storing":[132],"larger":[133],"number":[134],"excess":[136],"holes":[137],"in":[138,157],"longer":[143],"than":[145],"possible":[147],"with":[148],"cell.":[152],"We":[153],"report":[154],"improvement":[156],"well":[161,178],"sense":[163],"margin":[164],"both":[166],"T=300":[167,204,224],"K":[168,171,205,208,225,228],"T=358":[170,227],"our":[173],"through":[177],"calibrated":[179],"TCAD":[180],"simulations":[181],"[4].":[182],"extracted":[184],"source/drain":[194],"3.5":[198],"s":[199],"160":[201],"respectively":[209],"it":[216],"1.5":[218],"150":[221],"\u03bcs":[222],"respectively.":[229]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}