{"id":"https://openalex.org/W2889065131","doi":"https://doi.org/10.1109/drc.2018.8442170","title":"Epitaxial Gd<sub>2O</sub> <sub>3</sub>on Si (111) Substrate by Sputtering to Enable Low Cost SOI","display_name":"Epitaxial Gd<sub>2O</sub> <sub>3</sub>on Si (111) Substrate by Sputtering to Enable Low Cost SOI","publication_year":2018,"publication_date":"2018-06-01","ids":{"openalex":"https://openalex.org/W2889065131","doi":"https://doi.org/10.1109/drc.2018.8442170","mag":"2889065131"},"language":"en","primary_location":{"id":"doi:10.1109/drc.2018.8442170","is_oa":false,"landing_page_url":"https://doi.org/10.1109/drc.2018.8442170","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 76th Device Research Conference (DRC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5098564351","display_name":"Amlta","orcid":null},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Amlta","raw_affiliation_strings":["Indian Institute of Technology Bombay, India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Bombay, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076341079","display_name":"Krista R. Khiangte","orcid":"https://orcid.org/0000-0003-0294-7815"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"K. R. Khiangte","raw_affiliation_strings":["Indian Institute of Technology Bombay, India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Bombay, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006800683","display_name":"Apurba Laha","orcid":"https://orcid.org/0000-0001-7320-642X"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"A. Laha","raw_affiliation_strings":["Indian Institute of Technology Bombay, India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Bombay, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057107600","display_name":"Souvik Mahapatra","orcid":"https://orcid.org/0000-0002-4516-766X"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"S. Mahapatra","raw_affiliation_strings":["Indian Institute of Technology Bombay, India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Bombay, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059189948","display_name":"U. Gangway","orcid":null},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"U. Gangway","raw_affiliation_strings":["Indian Institute of Technology Bombay, India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Bombay, India","institution_ids":["https://openalex.org/I162827531"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5098564351"],"corresponding_institution_ids":["https://openalex.org/I162827531"],"apc_list":null,"apc_paid":null,"fwci":0.1288,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.48051483,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":93},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/epitaxy","display_name":"Epitaxy","score":0.5919271111488342},{"id":"https://openalex.org/keywords/silicon-on-insulator","display_name":"Silicon on insulator","score":0.45486611127853394},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.3535217046737671},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.34435969591140747},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3221549689769745},{"id":"https://openalex.org/keywords/silicon","display_name":"Silicon","score":0.2891652584075928},{"id":"https://openalex.org/keywords/nanotechnology","display_name":"Nanotechnology","score":0.25707054138183594},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.21384191513061523},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.20021280646324158},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10378265380859375}],"concepts":[{"id":"https://openalex.org/C110738630","wikidata":"https://www.wikidata.org/wiki/Q1135540","display_name":"Epitaxy","level":3,"score":0.5919271111488342},{"id":"https://openalex.org/C53143962","wikidata":"https://www.wikidata.org/wiki/Q1478788","display_name":"Silicon on insulator","level":3,"score":0.45486611127853394},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.3535217046737671},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.34435969591140747},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3221549689769745},{"id":"https://openalex.org/C544956773","wikidata":"https://www.wikidata.org/wiki/Q670","display_name":"Silicon","level":2,"score":0.2891652584075928},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.25707054138183594},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.21384191513061523},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.20021280646324158},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10378265380859375},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/drc.2018.8442170","is_oa":false,"landing_page_url":"https://doi.org/10.1109/drc.2018.8442170","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 76th Device Research Conference (DRC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W590399640","https://openalex.org/W3150448185"],"related_works":["https://openalex.org/W2935759653","https://openalex.org/W3105167352","https://openalex.org/W54078636","https://openalex.org/W2954470139","https://openalex.org/W1501425562","https://openalex.org/W2902782467","https://openalex.org/W3084825885","https://openalex.org/W2298861036","https://openalex.org/W3148032049","https://openalex.org/W2271181815"],"abstract_inverted_index":{"Silicon":[0],"on":[1],"insulator":[2],"(SOI)":[3],"enables":[4],"RF":[5],"technology":[6],"at":[7],"advanced":[8,157],"nodes":[9],"[1].":[10],"The":[11,31],"SOI-wafer":[12],"cost":[13],"is":[14,43,108],"the":[15],"key":[16],"challenge":[17],"due":[18,112],"to":[19,113,144],"complex":[20],"manufacturing":[21],"processes":[22],"such":[23,59],"as":[24,60],"\u201csmart":[25],"cut\u201d":[26],"or":[27],"wafer":[28],"bonding":[29],"[2].":[30],"epitaxial":[32],"growth":[33,42],"of":[34],"rare":[35],"earth":[36],"(RE)":[37],"oxides":[38,58],"followed":[39],"by":[40],"epi-Si":[41],"extensively":[44],"explored":[45],"for":[46,92,96,149],"SOI":[47],"stack":[48],"preparation.":[49],"Low":[50],"lattice":[51],"mismatch":[52],"(~0.5%)":[53],"between":[54],"Si":[55],"and":[56,152],"RE":[57],"Ce":[61],"<inf":[62,66,71,75,80,84,101,105,135,139],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[63,67,72,76,81,85,102,106,129,136,140],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</inf>":[64,73,82,103,137],"O":[65],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">3</inf>":[68,77,86,107,141],",":[69,78],"Pr":[70],"0":[74,83,104,138],"Gd":[79,100],"etc.":[87],"[3],":[88,118],"make":[89],"it":[90],"suitable":[91],"isolation":[93],"oxide":[94],"(IO)":[95],"SOI.":[97],"Among":[98],"all,":[99],"proven":[109],"most":[110],"promising,":[111],"stable":[114],"oxidation":[115],"state":[116],"(+3)":[117],"large":[119],"band":[120,126],"gap":[121],"(~5.9":[122],"eV)":[123],"and,":[124],"sufficient":[125],"offset":[127],"<tex":[128],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$(\\Delta":[130],"\\mathrm{E}_{\\mathrm{c}}=2.1\\mathrm{eV}\\&amp;\\Delta":[131],"\\mathrm{E}_{\\mathrm{v}}=2.8\\mathrm{eV})$</tex>":[132],"[4].":[133],"Epi-Gd":[134],"has":[142],"potential":[143],"be":[145],"an":[146],"attractive":[147],"alternative":[148],"gate":[150],"dielectric":[151],"IO":[153],"layer":[154],"[5]\u2013[8]":[155],"in":[156],"CMOS":[158],"technology.":[159]},"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}