{"id":"https://openalex.org/W1602788896","doi":"https://doi.org/10.1109/dftvs.2003.1250150","title":"A unified SOC test approach based on test data compression and TAM design","display_name":"A unified SOC test approach based on test data compression and TAM design","publication_year":2004,"publication_date":"2004-03-01","ids":{"openalex":"https://openalex.org/W1602788896","doi":"https://doi.org/10.1109/dftvs.2003.1250150","mag":"1602788896"},"language":"en","primary_location":{"id":"doi:10.1109/dftvs.2003.1250150","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dftvs.2003.1250150","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 16th IEEE Symposium on Computer Arithmetic","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019420188","display_name":"V. Iyengar","orcid":"https://orcid.org/0000-0001-6696-3940"},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"V. Iyengar","raw_affiliation_strings":["IBM Microelectronics, Essex Junction, VT, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM Microelectronics, Essex Junction, VT, USA","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041100073","display_name":"Anshuman Chandra","orcid":"https://orcid.org/0000-0002-2686-3918"},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Chandra","raw_affiliation_strings":["Synopsys, Inc., Mountain View, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Synopsys, Inc., Mountain View, CA, USA","institution_ids":["https://openalex.org/I4210088951"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"511","last_page":"518"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9868999719619751,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.7446855306625366},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.677941620349884},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6732203960418701},{"id":"https://openalex.org/keywords/test-data","display_name":"Test data","score":0.5897735953330994},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.5740092992782593},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.4898171126842499},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4782796800136566},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4677567481994629},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.4617678225040436},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4378967583179474},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3550716042518616},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18088731169700623}],"concepts":[{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.7446855306625366},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.677941620349884},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6732203960418701},{"id":"https://openalex.org/C16910744","wikidata":"https://www.wikidata.org/wiki/Q7705759","display_name":"Test data","level":2,"score":0.5897735953330994},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.5740092992782593},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.4898171126842499},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4782796800136566},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4677567481994629},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.4617678225040436},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4378967583179474},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3550716042518616},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18088731169700623},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dftvs.2003.1250150","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dftvs.2003.1250150","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 16th IEEE Symposium on Computer Arithmetic","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1496108890","https://openalex.org/W1536055443","https://openalex.org/W1570296235","https://openalex.org/W1863819993","https://openalex.org/W1915674790","https://openalex.org/W1960989085","https://openalex.org/W2057934715","https://openalex.org/W2103706706","https://openalex.org/W2107800433","https://openalex.org/W2108657959","https://openalex.org/W2109600608","https://openalex.org/W2133595845","https://openalex.org/W2144004661","https://openalex.org/W2146594632","https://openalex.org/W2148218783","https://openalex.org/W2151243068","https://openalex.org/W2162086806","https://openalex.org/W2165642910","https://openalex.org/W2166680980","https://openalex.org/W3136299071","https://openalex.org/W4230044641","https://openalex.org/W4254102020","https://openalex.org/W4255588132","https://openalex.org/W6683426328"],"related_works":["https://openalex.org/W2543176856","https://openalex.org/W2157212570","https://openalex.org/W3088373974","https://openalex.org/W1606802855","https://openalex.org/W1895064253","https://openalex.org/W2035832568","https://openalex.org/W2624668974","https://openalex.org/W3121464923","https://openalex.org/W2806771822","https://openalex.org/W2163486680"],"abstract_inverted_index":{"Test":[0],"access":[1],"mechanism":[2],"(TAM)":[3],"optimization":[4],"and":[5,17,49,88],"test":[6,14,37,44,50,63,72,85,91],"data":[7,15,51,80],"compression":[8],"lead":[9],"to":[10],"a":[11,35,95],"reduction":[12],"in":[13,62,84],"volume":[16,81],"testing":[18],"time":[19,30,87],"for":[20,27,94],"SOCs.":[21],"In":[22],"this":[23,102],"paper,":[24],"we":[25],"integrate":[26],"the":[28,70,89,99],"first":[29],"both":[31],"these":[32],"approaches":[33],"into":[34],"single":[36],"methodology.":[38],"We":[39],"show,":[40],"how":[41],"an":[42],"integrated":[43,71],"architecture":[45,73],"based":[46],"on":[47,78],"TAMs":[48],"decoders":[52],"can":[53],"be":[54],"designed.":[55],"The":[56],"proposed":[57],"approach":[58],"offers":[59],"considerable":[60],"savings":[61,83],"resource":[64],"requirements.":[65],"Two":[66],"case":[67],"studies":[68],"using":[69],"are":[74],"presented.":[75],"Experimental":[76],"results":[77],"rest":[79],"reduction,":[82],"application":[86],"low":[90],"pin":[92],"overheads":[93],"benchmark":[96],"SOC":[97],"demonstrate":[98],"effectiveness":[100],"of":[101],"approach.":[103]},"counts_by_year":[{"year":2014,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}