{"id":"https://openalex.org/W1593355900","doi":"https://doi.org/10.1109/dftvs.2003.1250089","title":"Yield analysis of compiler-based arrays of embedded SRAMs","display_name":"Yield analysis of compiler-based arrays of embedded SRAMs","publication_year":2004,"publication_date":"2004-03-02","ids":{"openalex":"https://openalex.org/W1593355900","doi":"https://doi.org/10.1109/dftvs.2003.1250089","mag":"1593355900"},"language":"en","primary_location":{"id":"doi:10.1109/dftvs.2003.1250089","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dftvs.2003.1250089","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 16th IEEE Symposium on Computer Arithmetic","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100689426","display_name":"Xinjun Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I12912129","display_name":"Northeastern University","ror":"https://ror.org/04t5xt781","country_code":"US","type":"education","lineage":["https://openalex.org/I12912129"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"X. Wang","raw_affiliation_strings":["Department of electrical and Computer Engineering, Northeastern University, USA","Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA"],"affiliations":[{"raw_affiliation_string":"Department of electrical and Computer Engineering, Northeastern University, USA","institution_ids":["https://openalex.org/I12912129"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA","institution_ids":["https://openalex.org/I12912129"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048232172","display_name":"Marco Ottavi","orcid":"https://orcid.org/0000-0002-5064-7342"},"institutions":[{"id":"https://openalex.org/I12912129","display_name":"Northeastern University","ror":"https://ror.org/04t5xt781","country_code":"US","type":"education","lineage":["https://openalex.org/I12912129"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Ottavi","raw_affiliation_strings":["Department of electrical and Computer Engineering, Northeastern University, USA","Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA"],"affiliations":[{"raw_affiliation_string":"Department of electrical and Computer Engineering, Northeastern University, USA","institution_ids":["https://openalex.org/I12912129"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA","institution_ids":["https://openalex.org/I12912129"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001979328","display_name":"Fabrizio Lombardi","orcid":"https://orcid.org/0000-0003-3152-3245"},"institutions":[{"id":"https://openalex.org/I12912129","display_name":"Northeastern University","ror":"https://ror.org/04t5xt781","country_code":"US","type":"education","lineage":["https://openalex.org/I12912129"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"F. Lombardi","raw_affiliation_strings":["Department of electrical and Computer Engineering, Northeastern University, USA","Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA"],"affiliations":[{"raw_affiliation_string":"Department of electrical and Computer Engineering, Northeastern University, USA","institution_ids":["https://openalex.org/I12912129"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA","institution_ids":["https://openalex.org/I12912129"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5100689426"],"corresponding_institution_ids":["https://openalex.org/I12912129"],"apc_list":null,"apc_paid":null,"fwci":1.0564,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.75298853,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"3","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.9042540192604065},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.8092679977416992},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7299634218215942},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.49603351950645447},{"id":"https://openalex.org/keywords/yield","display_name":"Yield (engineering)","score":0.4628196656703949},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.46153271198272705},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.43799978494644165},{"id":"https://openalex.org/keywords/optimizing-compiler","display_name":"Optimizing compiler","score":0.4162033200263977},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.38413259387016296},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3705750107765198},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.32235515117645264},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2714749574661255},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.20117276906967163},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13277173042297363},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09544086456298828}],"concepts":[{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.9042540192604065},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.8092679977416992},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7299634218215942},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.49603351950645447},{"id":"https://openalex.org/C134121241","wikidata":"https://www.wikidata.org/wiki/Q899301","display_name":"Yield (engineering)","level":2,"score":0.4628196656703949},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.46153271198272705},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.43799978494644165},{"id":"https://openalex.org/C190902152","wikidata":"https://www.wikidata.org/wiki/Q1325106","display_name":"Optimizing compiler","level":3,"score":0.4162033200263977},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.38413259387016296},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3705750107765198},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.32235515117645264},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2714749574661255},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.20117276906967163},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13277173042297363},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09544086456298828},{"id":"https://openalex.org/C191897082","wikidata":"https://www.wikidata.org/wiki/Q11467","display_name":"Metallurgy","level":1,"score":0.0},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/dftvs.2003.1250089","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dftvs.2003.1250089","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 16th IEEE Symposium on Computer Arithmetic","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.301.4759","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.301.4759","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://dftgroup.uniroma2.it/data/media/dft2003yield.pdf","raw_type":"text"},{"id":"pmh:oai:art.torvergata.it:2108/93767","is_oa":false,"landing_page_url":"http://hdl.handle.net/2108/93767","pdf_url":null,"source":{"id":"https://openalex.org/S4306400993","display_name":"Cineca Institutional Research Information System (Tor Vergata University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I116067653","host_organization_name":"University of Rome Tor Vergata","host_organization_lineage":["https://openalex.org/I116067653"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5099999904632568,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1867076631","https://openalex.org/W1973239387","https://openalex.org/W2016706393","https://openalex.org/W2021792911","https://openalex.org/W2041090186","https://openalex.org/W2083474207","https://openalex.org/W2105415532","https://openalex.org/W2105453813","https://openalex.org/W4235806833"],"related_works":["https://openalex.org/W2002505081","https://openalex.org/W2083681681","https://openalex.org/W2577630842","https://openalex.org/W1172579163","https://openalex.org/W1488300410","https://openalex.org/W2138790427","https://openalex.org/W3146558274","https://openalex.org/W4246454774","https://openalex.org/W2162051035","https://openalex.org/W1597127505"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,20,64,83],"detailed":[4],"analysis":[5,25,100],"of":[6,9,27,50,66,101],"the":[7,39,47,51,67,76,91,99],"yield":[8,92],"embedded":[10],"static":[11],"random":[12],"access":[13],"memories":[14],"(eSRAM)":[15],"which":[16,70],"are":[17,30,117],"generated":[18],"using":[19],"compiler.":[21],"Defect":[22],"and":[23,46,75,80,107,111],"fault":[24,73],"inclusive":[26],"industrial":[28,122],"data":[29,95],"presented":[31],"for":[32,72,98],"these":[33],"chips":[34],"by":[35,115],"taking":[36],"into":[37],"account":[38],"design":[40,68],"constructs":[41],"(referred":[42],"to":[43,89,121],"as":[44,113],"kernels)":[45],"physical":[48],"properties":[49],"layout.":[52],"The":[53,109],"new":[54],"tool":[55],"CAYA":[56,116],"(Compiler-based":[57],"Array":[58],"Yield":[59],"Analysis)":[60],"is":[61,87,96],"based":[62],"on":[63],"characterization":[65],"process":[69],"accounts":[71],"types":[74],"relation":[77],"between":[78],"functional":[79],"structural":[81],"faults;":[82],"novel":[84],"empirical":[85],"model":[86],"proposed":[88],"facilitate":[90],"calculation.":[93],"Industrial":[94],"provided":[97,114],"various":[102],"configurations":[103],"with":[104,119],"different":[105],"structures":[106],"redundancy.":[108],"effectiveness":[110],"accuracy":[112],"assessed":[118],"respect":[120],"designs.":[123]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
