{"id":"https://openalex.org/W2109828260","doi":"https://doi.org/10.1109/dftvs.2002.1173532","title":"Feasibility study of designing TSC sequential circuits with 100% fault coverage","display_name":"Feasibility study of designing TSC sequential circuits with 100% fault coverage","publication_year":2003,"publication_date":"2003-06-26","ids":{"openalex":"https://openalex.org/W2109828260","doi":"https://doi.org/10.1109/dftvs.2002.1173532","mag":"2109828260"},"language":"en","primary_location":{"id":"doi:10.1109/dftvs.2002.1173532","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dftvs.2002.1173532","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060281193","display_name":"S.J. Piestrak","orcid":"https://orcid.org/0000-0003-1248-106X"},"institutions":[{"id":"https://openalex.org/I11923345","display_name":"Wroc\u0142aw University of Science and Technology","ror":"https://ror.org/008fyn775","country_code":"PL","type":"education","lineage":["https://openalex.org/I11923345"]}],"countries":["PL"],"is_corresponding":true,"raw_author_name":"S.J. Piestrak","raw_affiliation_strings":["Institute of Engineering Cybernetics, Wroclaw University of Technology, Wroclaw, Poland","Inst. of Eng. Cybern., Wroclaw Univ. of Technol., Poland"],"affiliations":[{"raw_affiliation_string":"Institute of Engineering Cybernetics, Wroclaw University of Technology, Wroclaw, Poland","institution_ids":["https://openalex.org/I11923345"]},{"raw_affiliation_string":"Inst. of Eng. Cybern., Wroclaw Univ. of Technol., Poland","institution_ids":["https://openalex.org/I11923345"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5060281193"],"corresponding_institution_ids":["https://openalex.org/I11923345"],"apc_list":null,"apc_paid":null,"fwci":0.5031,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.66283488,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"2","issue":null,"first_page":"354","last_page":"362"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.707487165927887},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.659044623374939},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6273688077926636},{"id":"https://openalex.org/keywords/principal","display_name":"Principal (computer security)","score":0.6161651611328125},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.5818257331848145},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.44432106614112854},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.43442827463150024},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.4260202944278717},{"id":"https://openalex.org/keywords/fault-detection-and-isolation","display_name":"Fault detection and isolation","score":0.4155150353908539},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3566195070743561},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.27416688203811646},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1761280596256256},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.09738942980766296},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08733072876930237},{"id":"https://openalex.org/keywords/computer-security","display_name":"Computer security","score":0.08532556891441345}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.707487165927887},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.659044623374939},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6273688077926636},{"id":"https://openalex.org/C144559511","wikidata":"https://www.wikidata.org/wiki/Q2986279","display_name":"Principal (computer security)","level":2,"score":0.6161651611328125},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.5818257331848145},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.44432106614112854},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.43442827463150024},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.4260202944278717},{"id":"https://openalex.org/C152745839","wikidata":"https://www.wikidata.org/wiki/Q5438153","display_name":"Fault detection and isolation","level":3,"score":0.4155150353908539},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3566195070743561},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.27416688203811646},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1761280596256256},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.09738942980766296},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08733072876930237},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.08532556891441345},{"id":"https://openalex.org/C172707124","wikidata":"https://www.wikidata.org/wiki/Q423488","display_name":"Actuator","level":2,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dftvs.2002.1173532","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dftvs.2002.1173532","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.699999988079071,"display_name":"Peace, Justice and strong institutions","id":"https://metadata.un.org/sdg/16"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1565209918","https://openalex.org/W1766829730","https://openalex.org/W1980902510","https://openalex.org/W2047207707","https://openalex.org/W2086059614","https://openalex.org/W2120653184","https://openalex.org/W2130969484","https://openalex.org/W2131105156","https://openalex.org/W2152805280","https://openalex.org/W2162953658","https://openalex.org/W6679753974"],"related_works":["https://openalex.org/W2989159162","https://openalex.org/W2153201966","https://openalex.org/W2122754719","https://openalex.org/W2139513292","https://openalex.org/W1982569681","https://openalex.org/W776711554","https://openalex.org/W1874778078","https://openalex.org/W2536854812","https://openalex.org/W2005858638","https://openalex.org/W3147816099"],"abstract_inverted_index":{"Several":[0],"design":[1],"methods":[2,21],"of":[3,18,41,61,74],"self-checking":[4,77],"synchronous":[5],"sequential":[6],"circuits":[7],"(SMs)":[8],"have":[9],"been":[10],"proposed":[11],"in":[12],"the":[13,24,34,72],"literature.":[14],"Two":[15],"principal":[16],"drawbacks":[17],"all":[19],"these":[20],"are:":[22],"1)":[23],"internal":[25,49],"fault":[26,88],"coverage":[27],"rarely":[28],"equals":[29],"to":[30,37,45],"100%":[31,87],"and":[32],"2)":[33],"checkers":[35],"used":[36],"monitor":[38],"correct":[39],"operation":[40,57],"a":[42,59],"SM":[43],"(claimed":[44],"be":[46,53],"self-testing)":[47],"contain":[48],"faults":[50],"which":[51],"cannot":[52],"detected":[54],"during":[55],"normal":[56],"by":[58],"subset":[60],"codewords":[62],"which,":[63],"are":[64],"actually":[65],"used.":[66],"In":[67],"this":[68],"paper,":[69],"we":[70],"analyze":[71],"possibility":[73],"designing":[75],"totally":[76],"(TSC)":[78],"SMs":[79],"protected":[80],"against":[81],"errors":[82],"using":[83],"unordered":[84],"codes":[85],"with":[86],"coverage.":[89]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
